Talk:GIGABYTE GA-M57SLI-S4: Difference between revisions
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'''badly in need:''' | |||
* is it practical to upgrade the secondary pad with an 2 MBit flash part ? | |||
''2 MByte:'' the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check. | |||
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[http://sites.google.com/site/pinczakko/pinczakko-s-guide-to-ami-bios-reverse-engineering-1 Salihun] on '''AWARD''' ('legacy') BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI. | |||
Latest revision as of 07:03, 2 December 2010
swap #CE and #WP and thus route #CE through the #WP jumper with 8 pin SPI possible ? --da Great QUUX 14:24, 28 April 2007 (CEST)
Alternatively, you might flip a standard plcc-32 socket over the mainboard-chip. then wire a secondary plcc-32 socket to it wired 1:1 - except you connect /reset and /oe on the replacment chip, while you route the /oe from the mainboard to an NC pin on the secondary chip. Take off (hot unplug) the socket after successful boot-up to reflash the original chip. (so called "top hat flash" method, use at own risk, no successful report on GA M57 yet)
on GA M57SLI, is FWH mode used ? is it necessary to use different ID on ID-pins ?
badly in need:
- is it practical to upgrade the secondary pad with an 2 MBit flash part ?
2 MByte: the southbridge needs to decode the full 2Mbyte (these are 16Mbit parts) address range for it to be useful in practice. A lot of the SB parts I looked at, years ago, reserved the top 2M of the 2 GB space. so it is something we have to check.
Salihun on AWARD ('legacy') BIOS re-engineering. AWARD is inside many boards by Gigabyte like M57SLI.