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I'm [http://www.hailfinger.org/ Carl-Daniel Hailfinger]. | I'm [http://www.hailfinger.org/ Carl-Daniel Hailfinger]. | ||
This page is very outdated (it still mentions LinuxBIOS and v2). One day I'll have time to update it. | |||
My LinuxBIOS/coreboot-related interests and contributions are | My LinuxBIOS/coreboot-related interests and contributions are | ||
* flashrom SPI support (I wrote all SPI support code) and generic flash chip support | * flashrom. I'm the de facto release engineer and organizer. My specialties are architecture, SPI support (I wrote all SPI support code), external flasher infrastructure, verification and generic flash chip support. | ||
* superiotool support | * superiotool support | ||
* coreboot v3 design and restructuring work as well as board support. | * coreboot v3 design and restructuring work as well as board support | ||
* porting coreboot v3 code to v2. | |||
I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. | I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. Updating v2 to use as much v3 code as possible is one of the ways to achieve this goal. | ||
Legal disclaimer: My opinions do not represent the opinions of the coreboot project. | Legal disclaimer: My opinions do not represent the opinions of the coreboot project. | ||
==Useful coreboot knowledge== | |||
===Build problems found by the BSI coreboot lab=== | |||
* Qemu Q35 normal image fails to compile. Fix: [https://review.coreboot.org/#/c/12574/] | |||
* Replacing existing files in the cbfs image during build fails. Fix: [https://review.coreboot.org/#/c/12581/] | |||
===Not completely debugged hardware issues found by the BSI coreboot lab=== | |||
* x220 spontaneous early reboot | |||
Latest revision as of 19:20, 20 December 2015
This page is very outdated (it still mentions LinuxBIOS and v2). One day I'll have time to update it.
My LinuxBIOS/coreboot-related interests and contributions are
- flashrom. I'm the de facto release engineer and organizer. My specialties are architecture, SPI support (I wrote all SPI support code), external flasher infrastructure, verification and generic flash chip support.
- superiotool support
- coreboot v3 design and restructuring work as well as board support
- porting coreboot v3 code to v2.
I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. Updating v2 to use as much v3 code as possible is one of the ways to achieve this goal.
Legal disclaimer: My opinions do not represent the opinions of the coreboot project.
Useful coreboot knowledge
Build problems found by the BSI coreboot lab
- Qemu Q35 normal image fails to compile. Fix: [1]
- Replacing existing files in the cbfs image during build fails. Fix: [2]
Not completely debugged hardware issues found by the BSI coreboot lab
- x220 spontaneous early reboot