Board:intel/d945gclf: Difference between revisions
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The d945gclf2 is almost the same board as d945gclf but with a dual core CPU instead of a single core, an extra USB header and a gigabit | The d945gclf2 is almost the same board as the d945gclf, but with a dual core CPU instead of a single core, an extra USB header and a gigabit network card instead of a 10/100. This board also works fine with coreboot. | ||
== Status == | == SeaBIOS ATA DMA == | ||
By default, SeaBIOS uses PIO mode for ATA interfaces. On the ICH7 southbridge, this is very slow. Loading a kernel + initramfs can take up to 20 seconds on this board. | |||
When using ATA DMA mode, this bug disappears. This will have to be set explicitly in the SeaBIOS config file, and selected from coreboot's menuconfig. | |||
From the coreboot root directory, go to ''payloads/external/SeaBIOS/seabios'': | |||
<syntaxhighlight lang="bash" inline>cd payloads/external/SeaBIOS/seabios/</syntaxhighlight> | |||
Create a file called ''.config'' and add these lines to it: | |||
CONFIG_COREBOOT=y | |||
CONFIG_ATA_DMA=y | |||
CONFIG_VGA_COREBOOT=y | |||
Then, create a full ''.config'' file by running: | |||
<syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight> | |||
Navigate to '''General Features''' and make sure the ''Build Target'' is set to ''Build for coreboot''. | |||
Navigate to '''Hardware support''' and make sure that ''ATA DMA'' is ''enabled'' [*]. | |||
Navigate to '''VGA ROM''' and make sure that ''VGA Hardware Type'' is set to ''coreboot linear framebuffer''. | |||
Exit menuconfig and save the changes. | |||
It is probably easiest to move the ''.config'' file to the coreboot root directory, under a different name (e.g. ''.seabiosconfig''), as coreboot already has its own ''.config'' file. | |||
<syntaxhighlight lang="bash" inline>mv .config ../../../../.seabiosconfig</syntaxhighlight> | |||
Finally return to the coreboot root directory: | |||
<syntaxhighlight lang="bash" inline>cd ../../../../</syntaxhighlight> | |||
== coreboot configuration == | |||
Create a file called ''.config'' and add at least these lines to it: | |||
CONFIG_VENDOR_INTEL=y | |||
CONFIG_BOARD_INTEL_D945GCLF=y | |||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y | |||
CONFIG_USE_OPTION_TABLE=y | |||
In case you '''do not''' want CPU microcode updates included in your ROM, add this line: | |||
CONFIG_CPU_MICROCODE_CBFS_NONE=y | |||
In case you '''do''' want to include CPU microcode updates in your ROM, add these lines: | |||
CONFIG_USE_BLOBS=y | |||
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y | |||
By default, serial debugging output is enabled. It is very useful for debugging, but also slows down the boot process a lot. If you don't need serial debug or have no idea how to use it, disable it: | |||
CONFIG_CONSOLE_SERIAL=n | |||
Then, create a full ''.config'' file by running: | |||
<syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight> | |||
Navigate to '''General setup''' and make sure that ''Use CMOS for configuration values'' is ''enabled'' [*]. | |||
Navigate to '''Mainboard''' and make sure the ''Mainboard vendor'' is set to ''INTEL'' and the ''Mainboard model'' to ''D945GCLF''. | |||
Navigate to '''Chipset''' and make sure that ''Include CPU microcode in CBFS'' is set to either ''Generate from tree'' or ''Do not include microcode updates''. | |||
* In case you selected ''Generate from tree'', make sure that '''General setup''' -> ''Allow use of binary-only repository'' is ''enabled'' [*]. | |||
Navigate to '''Devices''' and make sure that ''Use native graphics initialization'' is ''enabled'' [*]. | |||
Navigate to '''Payload''' and set your SeaBIOS configuration in ''SeaBIOS config file''. | |||
* This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ''~/Downloads/coreboot/.seabiosconfig'' | |||
Exit menuconfig and save the changes. | |||
Now build your ROM: | |||
<syntaxhighlight lang="bash" inline>make</syntaxhighlight> | |||
== CMOS default values == | |||
By default, the VGA shared RAM on this board is set to 8MB. While this is fine for server use, this is not ideal for desktop or HTPC use. | |||
In order to change CMOS defaults, you will need '''nvramtool''': | |||
<syntaxhighlight lang="bash" inline>cd util/nvramtool/ | |||
make | |||
mv nvramtool ../../nvramtool | |||
cd ../../ | |||
</syntaxhighlight> | |||
The VGA shared RAM can be increased to 16MB, 32MB or 64MB by running: | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=16M</syntaxhighlight> | |||
or | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=32M</syntaxhighlight> | |||
or | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=64M</syntaxhighlight> | |||
== Backing up the vendor BIOS == | |||
This board can be flashed with flashrom, which is in the repositories of nearly every GNU/Linux distribution. | |||
However, the Intel vendor BIOS locks writes to the chip from a running system, ''so you can only flash internally if you are already running coreboot.'' | |||
To make a backup of the BIOS chip, run: | |||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal -r bios.rom</syntaxhighlight> | |||
== Internal flashing == | |||
To flash the BIOS chip, run: | |||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal -w build/coreboot.rom</syntaxhighlight> | |||
As stated above, writing to the chip is only possible when running coreboot. The inital flash will have to be done externally. | |||
== External flashing == | |||
== Chip pinout == | |||
_______________ | |||
-cs vcc- | |||
-miso - | |||
- clk- | |||
-gnd mosi- | |||
_______________ | |||
== Status (as of commit 5360c7ef94) == | |||
{{Status| | {{Status| | ||
Line 11: | Line 133: | ||
|CPU_L2_status = OK | |CPU_L2_status = OK | ||
|CPU_L3_status = N/A | |CPU_L3_status = N/A | ||
|CPU_virt_status = | |CPU_virt_status = N/A | ||
|CPU_multicore_status = OK | |CPU_multicore_status = OK | ||
|CPU_multiple_status = N/A | |CPU_multiple_status = N/A | ||
Line 24: | Line 146: | ||
|IDE_status = Untested | |IDE_status = Untested | ||
|IDE_25_status = | |IDE_25_status = N/A | ||
|SATA_status = OK | |SATA_status = OK | ||
|USB_status = OK | |USB_status = OK | ||
|Onboard_VGA_status = OK | |Onboard_VGA_status = OK | ||
|Onboard_VGA_comments = VBIOS works. Only textmode available for native graphic init | |Onboard_VGA_comments = VBIOS works. Only textmode available for native graphic init. | ||
|Onboard_ethernet_status = OK | |Onboard_ethernet_status = OK | ||
|Onboard_audio_status = OK | |Onboard_audio_status = OK | ||
Line 53: | Line 175: | ||
|HTX_status = N/A | |HTX_status = N/A | ||
|Floppy_status = | |Floppy_status = N/A | ||
|COM1_status = OK | |COM1_status = OK | ||
|COM2_status = | |COM2_status = N/A | ||
|PP_status = Untested | |PP_status = Untested | ||
|PS2_keyboard_status = OK | |PS2_keyboard_status = OK | ||
Line 67: | Line 189: | ||
|Watchdog_status = Unknown | |Watchdog_status = Unknown | ||
|CAN_bus_status = N/A | |CAN_bus_status = N/A | ||
|CPUfreq_status = | |CPUfreq_status = N/A | ||
|Powersave_status = | |Powersave_status = N/A | ||
|ACPI_status = OK | |ACPI_status = OK | ||
|SMBus_status = OK | |SMBus_status = OK | ||
Line 75: | Line 197: | ||
|Suspend_status = OK | |Suspend_status = OK | ||
|LEDs_status = OK | |LEDs_status = OK | ||
|HPET_status = | |HPET_status = OK | ||
|RNG_status = N/A | |RNG_status = N/A | ||
|WakeOnModem_status = N/A | |||
|WakeOnLAN_status = OK | |||
|WakeOnLAN_comments = Tested on d945gclf only. | |||
|WakeOnKeyboard_status = Unknown | |||
|WakeOnMouse_status = Unknown | |||
|Flashrom_status = OK | |Flashrom_status = OK | ||
|Flashrom_comments = | |Flashrom_comments = Needs external flashing from vendor BIOS, internal works fine on coreboot. | ||
}} | }} |
Latest revision as of 23:02, 27 February 2017
This page describes how to use coreboot on the Intel d945gclf mainboard.
The d945gclf2 is almost the same board as the d945gclf, but with a dual core CPU instead of a single core, an extra USB header and a gigabit network card instead of a 10/100. This board also works fine with coreboot.
SeaBIOS ATA DMA
By default, SeaBIOS uses PIO mode for ATA interfaces. On the ICH7 southbridge, this is very slow. Loading a kernel + initramfs can take up to 20 seconds on this board.
When using ATA DMA mode, this bug disappears. This will have to be set explicitly in the SeaBIOS config file, and selected from coreboot's menuconfig.
From the coreboot root directory, go to payloads/external/SeaBIOS/seabios: <syntaxhighlight lang="bash" inline>cd payloads/external/SeaBIOS/seabios/</syntaxhighlight>
Create a file called .config and add these lines to it:
CONFIG_COREBOOT=y CONFIG_ATA_DMA=y CONFIG_VGA_COREBOOT=y
Then, create a full .config file by running: <syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight>
Navigate to General Features and make sure the Build Target is set to Build for coreboot.
Navigate to Hardware support and make sure that ATA DMA is enabled [*].
Navigate to VGA ROM and make sure that VGA Hardware Type is set to coreboot linear framebuffer.
Exit menuconfig and save the changes.
It is probably easiest to move the .config file to the coreboot root directory, under a different name (e.g. .seabiosconfig), as coreboot already has its own .config file.
<syntaxhighlight lang="bash" inline>mv .config ../../../../.seabiosconfig</syntaxhighlight>
Finally return to the coreboot root directory: <syntaxhighlight lang="bash" inline>cd ../../../../</syntaxhighlight>
coreboot configuration
Create a file called .config and add at least these lines to it:
CONFIG_VENDOR_INTEL=y CONFIG_BOARD_INTEL_D945GCLF=y CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_USE_OPTION_TABLE=y
In case you do not want CPU microcode updates included in your ROM, add this line:
CONFIG_CPU_MICROCODE_CBFS_NONE=y
In case you do want to include CPU microcode updates in your ROM, add these lines:
CONFIG_USE_BLOBS=y CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
By default, serial debugging output is enabled. It is very useful for debugging, but also slows down the boot process a lot. If you don't need serial debug or have no idea how to use it, disable it:
CONFIG_CONSOLE_SERIAL=n
Then, create a full .config file by running: <syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight>
Navigate to General setup and make sure that Use CMOS for configuration values is enabled [*].
Navigate to Mainboard and make sure the Mainboard vendor is set to INTEL and the Mainboard model to D945GCLF.
Navigate to Chipset and make sure that Include CPU microcode in CBFS is set to either Generate from tree or Do not include microcode updates.
- In case you selected Generate from tree, make sure that General setup -> Allow use of binary-only repository is enabled [*].
Navigate to Devices and make sure that Use native graphics initialization is enabled [*].
Navigate to Payload and set your SeaBIOS configuration in SeaBIOS config file.
- This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ~/Downloads/coreboot/.seabiosconfig
Exit menuconfig and save the changes.
Now build your ROM:
<syntaxhighlight lang="bash" inline>make</syntaxhighlight>
CMOS default values
By default, the VGA shared RAM on this board is set to 8MB. While this is fine for server use, this is not ideal for desktop or HTPC use.
In order to change CMOS defaults, you will need nvramtool: <syntaxhighlight lang="bash" inline>cd util/nvramtool/ make mv nvramtool ../../nvramtool cd ../../ </syntaxhighlight>
The VGA shared RAM can be increased to 16MB, 32MB or 64MB by running:
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=16M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=32M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=64M</syntaxhighlight>
Backing up the vendor BIOS
This board can be flashed with flashrom, which is in the repositories of nearly every GNU/Linux distribution.
However, the Intel vendor BIOS locks writes to the chip from a running system, so you can only flash internally if you are already running coreboot.
To make a backup of the BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal -r bios.rom</syntaxhighlight>
Internal flashing
To flash the BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal -w build/coreboot.rom</syntaxhighlight>
As stated above, writing to the chip is only possible when running coreboot. The inital flash will have to be done externally.
External flashing
Chip pinout
_______________ -cs vcc- -miso - - clk- -gnd mosi- _______________
Status (as of commit 5360c7ef94)
Device/functionality | Status | Comments | ||||||
---|---|---|---|---|---|---|---|---|
CPU | ||||||||
CPU works | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L1 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L2 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L3 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multiple CPU support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multi-core support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Hardware virtualization | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
RAM | ||||||||
EDO | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SDRAM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SO-DIMM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR2 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
DDR3 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Dual channel support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
ECC support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Hardware | ||||||||
On-board IDE 3.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
On-board IDE 2.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board SATA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board SCSI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | VBIOS works. Only textmode available for native graphic init. | ||||||
On-board Ethernet | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Modem | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board FireWire | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Smartcard reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board CompactFlash | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board PCMCIA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Wifi | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Bluetooth | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board SD card reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Add-on slots/cards | ||||||||
ISA add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Audio/Modem-Riser (AMR/CNR) cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Mini-PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Mini-PCI-Express add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
PCI-X add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
AGP graphics cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x1 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x2 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x4 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x8 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x16 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x32 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
HTX add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Legacy / Super I/O | ||||||||
Floppy | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Serial port 1 (COM1) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Serial port 2 (COM2) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Parallel port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
PS/2 keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
PS/2 mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
Game port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Infrared | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PC speaker | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DiskOnChip | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Input | ||||||||
Trackpoint | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Touchpad | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fn Hotkeys | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fingerprint Reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Laptop | ||||||||
Docking VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Displayport | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Thinklight | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Webcam | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Miscellaneous | ||||||||
Sensors / fan control | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Hardware watchdog | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
SMBus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
CAN bus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
CPU frequency scaling | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Other powersaving features | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
ACPI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Reboot | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Poweroff | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Suspend | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Nonstandard LEDs | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
High precision event timers (HPET) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Random number generator (RNG) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Wake on modem ring | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Wake on LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Tested on d945gclf only. | ||||||
Wake on keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Wake on mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
TPM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Flashrom | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Needs external flashing from vendor BIOS, internal works fine on coreboot. |