Board:lenovo/x200: Difference between revisions

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* Dock
* Dock
* Digitizer on x200t variant
* Digitizer on x200t variant
 
* Modem
Untested:
* Modem (probably works)


== X200S and X200 Tablet ==
== X200S and X200 Tablet ==
These use the GS45 chipset which is very similar to GM45 chipset that the X200 uses. Boards with the SL* CPUs (so-called "high-performance") are compatible with GM45, and can be enabled in coreboot.
[http://review.coreboot.org/#/c/7786/ This patch on gerrit] enables GS45 chipset and makes the X200S or X200 Tablet work, if it has the "high-performance" CPU. SL model (CPU) is compatible, SU is not.


Both the X200S and X200 Tablet use a WSON-8 package for the flash chip. This has the same pinout as a SOIC-8 flash chip, but you will need to solder some (very thin) wires to a pin header since no clips are available for this type of connection.
Both the X200S and X200 Tablet use a WSON-8 package for the flash chip. This has the same pinout as a SOIC-8 flash chip, but you will need to solder some (very thin) wires to a pin header since no clips are available for this type of connection.
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'''<small>note 1:</small>'''
'''<small>note 1:</small>'''


Many machines were tested without it and did not show any issues that most users would notice. The only minor issue reported by 1 user is that vt-x (hardware-assisted virtualization) stopped working without the update, but otherwise the machine boots and works reliably.
VT-x (hardware-assisted virtualization) stops working without microcode updates.
 
The laptop will randomly and sporadically crash without microcode updates. The conditions under which these crashes occur at currently not known.
'''<small>note 2:</small>'''
 
Text-mode native gfx init is currently broken on the X200, but framebuffer mode (what most people use) works. This will need to be investigated.


== Dumping the original firmware ==
== Dumping the original firmware ==
Line 139: Line 130:
You cannot simply build the image and flash it, without first including several other "regions" that are discussed below.
You cannot simply build the image and flash it, without first including several other "regions" that are discussed below.


=== With ME/AMT ===
The easiest way to handle the non-coreboot blobs that need to be present on flash is by using flashrom 1.0 or later.
 
The following method involves extracting the descriptor, Gbe, ME and Platform regions from the original firmware and placing them (unmodified) inside the coreboot image.
 
In this setup, every region is present:
* Descriptor - copied from original firmware (config data, describes regions in the boot flash and so on)
* ME - copied from original firmware (intel management engine. huge blob. can be removed, see next section)
* Gbe - copied from original firmware (configuration data for the onboard ethernet chipset, also contains your MAC address)
* Platform - copied from original firmware (contents unknown)
* BIOS (where coreboot goes)
 
For the 8MiB flash chip:
 
* Recover the descriptor, me, gbe and platform data:
  dd if=flash.bin of=descriptor_me.bin count=6 bs=1M
* Compile coreboot
* Put descriptor and me back:
  dd if=descriptor_me.bin of=build/coreboot.rom bs=1M conv=notrunc
 
For the 4MiB flash chip:


* Recover the descriptor, me, gbe and platform data:
=== With ME firmware updates/AMT ===
  dd if=flash.bin of=descriptor_me.bin count=2 bs=1M
* Compile coreboot
* Put descriptor and me back:
  dd if=descriptor_me.bin of=build/coreboot.rom bs=1M conv=notrunc
 
* Flash the resulting build/coreboot.rom. If it fails due to interference, then try again many times until it works.


=== Without ME/AMT ===
With flashrom 1.0 or later you don't need to extract any blob from the vendor image, you can just leave them where they are, which is highly recommended!


It is possible to boot without the ME, by using a modified descriptor region.
First of all make a backup with your external programmer and verify it be a proper image.
<pre>
flashrom -p "external_programmer" -r vendor.rom && flashrom -p "external_programmer" -v vendor.rom
</pre>


The ME is a potential security and privacy risk, so removing it is preferable. Removing it also means that the BIOS region can fill most of the flash chip, giving plenty of flashing space (example use-case scenario: BusyBox+Linux system in SPI flash, to be used as a live rescue system).
After having successfully made a backup of you vendor firmware it is time to flash the coreboot image you build:
<pre>
flashrom -p "external_programmer" -w coreboot.rom --ifd --image bios --noverify-all
</pre>
and done!


Download the libreboot source code at [http://libreboot.org/docs/release.html the release page] or the metadata through git (git clone http://libreboot.org/libreboot.git) and
To update the coreboot image later on do the following:
you will find ich9gen under resources/utilities/ich9deblob/. Alternatively, ich9gen is included statically compiled in the binary releases under ./ich9deblob/
<pre>
flashrom -p internal -w coreboot.rom --ifd --image bios
</pre>


Use the ich9gen utility from the libreboot project, to generate a descriptor and Gbe region (the utility generates them from scratch, without needing a factory.rom dump). In this setup, the following regions are enabled:
=== Without ME firmware updates/AMT ===


* Descriptor (4K) - data created in ich9gen goes here (config data, describes regions in the boot flash, etc)
On this hardware it is possible to ommit the ME firmware updates while still using the Intel firmware descriptor + GBE region.
* Gbe (8K) - data created in ich9gen goes here (config data for the onboard ethernet chipset, also contains your MAC address)
This make it possible to use the flash region the ME used for bios region, allowing for much larger payloads (useful for Linux payloads).
* BIOS (8180K or 4084K, depending on whether the machine has a 4MiB or 8MiB flash chip) - coreboot goes here
This requires the use a modified descriptor and moving things around a bit.


In menuconfig, set the size of CBFS (in bytes, in hex) to 8MiB - 12KiB, or 4MB - 12KiB depending on whether you have a 4MiB or 8MiB flash chip.  
First of all make a backup with your external programmer and verify it be a proper image.
<pre>
flashrom -p "external_programmer" -r vendor.rom && flashrom -p "external_programmer" -v vendor.rom
</pre>


Note your machines current MAC address (for the onboard ethernet chipset) and keep this information safe. It should be printed below the DDR3 modules, which are accessible by removing two screws and a door on the underside of the machine.
There is a tool to generate a modified flash descriptor: 'blobtool'
go to util/blobtool:


Build your coreboot image as usual, and generate the 12KiB descriptor+gbe file as follows (replace the XX characters with those from your MAC address):
<pre>
./ich9gen --macaddress XX:XX:XX:XX:XX:XX
make
./blobtool ifd-x200.spec ifd-x200.set ifd.bin
</pre>


The files ich9fdgbe_8m.bin and ich9fdgbe_4m.bin will have been generated by ich9gen.
if your flash is not 8M modify ifd-x200.set
e.g. 4M


For the 8MiB flash chip:
<pre>
  dd if=ich9fdgbe_8m.bin of=build/coreboot.rom bs=1 count=12k conv=notrunc
diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set
For the 4MiB flash chip:
index 255eb88b70..25ae281906 100644
dd if=ich9fdgbe_4m.bin of=build/coreboot.rom bs=1 count=12k conv=notrunc
--- a/util/blobtool/ifd-x200.set
+++ b/util/blobtool/ifd-x200.set
@@ -35,7 +35,7 @@
        "flmap2_msl" = 0x1,
        "flmap2_reserved" = 0x0,
   
-      "flcomp_density1" = 0x4,
+      "flcomp_density1" = 0x3,
        "flcomp_density2" = 0x2,
        "flcomp_reserved0" = 0x0,
        "flcomp_reserved1" = 0x0,
@@ -56,7 +56,7 @@
        "flreg0_reserved1" = 0x0,
        "flreg1_base" = 0x3,
        "flreg1_reserved0" = 0x0,
-      "flreg1_limit" = 0x7ff,
+      "flreg1_limit" = 0x3ff,
        "flreg1_reserved1" = 0x0,
        "flreg2_base" = 0x1fff,
        "flreg2_reserved0" = 0x0,
</pre>


ich9gen is available in libreboot binary releases as static binaries, or as source under resources/utilities/ich9deblob/ under libreboot src or git.
or for 16M flash


More information about ich9gen at the [http://libreboot.org/docs/hcl/gm45_remove_me.html#ich9gen libreboot project website]
<pre>
diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set
index 255eb88b70..bbcb159616 100644
--- a/util/blobtool/ifd-x200.set
+++ b/util/blobtool/ifd-x200.set
@@ -35,7 +35,7 @@
        "flmap2_msl" = 0x1,
        "flmap2_reserved" = 0x0,
-      "flcomp_density1" = 0x4,
+      "flcomp_density1" = 0x5,
        "flcomp_density2" = 0x2,
        "flcomp_reserved0" = 0x0,
        "flcomp_reserved1" = 0x0,
@@ -56,7 +56,7 @@
        "flreg0_reserved1" = 0x0,
        "flreg1_base" = 0x3,
        "flreg1_reserved0" = 0x0,
-      "flreg1_limit" = 0x7ff,
+      "flreg1_limit" = 0x1fff,
        "flreg1_reserved1" = 0x0,
        "flreg2_base" = 0x1fff,
        "flreg2_reserved0" = 0x0,
</pre>


Libreboot also distributes pre-compiled X200 ROM images in the binary archive, built from libreboot sources with the descriptor
Now let's start by flashing this descriptor.
and Gbe already included inside the ROM images (generated from ich9gen, so no ME). However, do note that the Gbe region will contain a default MAC address
It first needs some padding since as of writing flashrom still needs image that match the whole flash size even if only a
other than what you probably want to use. (generate a new descriptor+gbe image using --macaddress in ich9gen and put in in the ROM, as mentioned above).
region is flashed.


After doing this, the ROM images will have a correct Gbe region inside containing your MAC address.
modify '8' in the command to create your flash by your flash size in MB.
<pre>
dd if=/dev/zero of=padding.bin bs=$((8 * 1024 * 1024 - 4096)) count=1
cat ifd.bin padding.bin > ifd_8M.bin
flashrom -p "external_programmer" -w ifd_8M.bin --ifd --image fd --noverify-all
</pre>


By default, the ich9gen utility generates a descriptor with all regions writeable from the Host CPU / BIOS. You can optionally write-protect
Given that the GBE region is a different offset compared to vendor, we need to move it around too.
the flash chip (or select regions) by modifying ich9gen; see src/ich9gen/mkdescriptor.c. '''If you write-protect your flash chip, it will mean that external flashing is needed later on when you want to re-flash those regions.'''
First extract it from the vendor image:
<pre>
ifdtool vendor.rom -x
</pre>


You can learn about the descriptor/Gbe region contents by reading the ich9gen/ich9deblob source code in libreboot under resources/utilities/ich9deblob/
Now inject the GBE region into the previously created ifd_8M.bin and flash it to the SPI flash.
<pre>
ifdtool -i GBE:flashregion_3_gbe.bin ifd_8M.bin
flashrom -p "external_programmer" -w ifd_8M.bin.new --ifd --image gbe --noverify-all
</pre>
Now finally we can flash our coreboot image. Notice that when building coreboot CONFIG_CBFS_SIZE can now
be safely set to 0x7fd000 (8 * 1024 * 1024 - 4096 - 8192) for 8M flash to make a maximal use of the available flash:


==== Write-protecting the (entire) flash chip ====
<pre>
flashrom -p "external_programmer" -w coreboot.rom --ifd --image bios --noverify-all
</pre>


Prevent possible malware in your OS from re-writing the flash chip contents (make external flashing required).
On future coreboot updates (no need for external programmer now) simply never touch the other regions again:
 
<pre>
Copied from [http://libreboot.org/gitdocs/hcl/gm45_remove_me.html#ich9gen libreboot documentation]:
flashrom -p internal -w coreboot.rom --ifd --image bios
 
</pre>
Look in resources/utilities/ich9deblob/src/descriptor/descriptor.c (in libreboot) for the following lines in the descriptorHostRegionsUnlocked function:
 
  descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1;
  descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1;
  descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1;
  descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1;
  descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1;
 
Change them all to 0x0, then re-compile ich9gen. After you have done that, follow the instructions to generate a new descriptor+gbe image and insert that into your ROM image, then flash it. The next time you boot, the flash chip will be read-only in software (hardware re-flashing will still work, which you will need for re-flashing the chip after write-protecting it, to clear the write protection or to flash yet another ROM image with write protection set in the descriptor).


== Internal flashing ==
== Internal flashing ==
Line 232: Line 265:
Once coreboot is installed and running, internal flashing should be easier.
Once coreboot is installed and running, internal flashing should be easier.


If the read/write bits in flmstr1 (see ich9gen src) are all set to 1, it means that '''-p internal''' in flashrom should work such that re-flashing in hardware is no longer necessary.  
Either generate a layout using ifdtool to only flash the bios region, or use flashrom 1.0 or later to read the layout from the Firmware Descriptor on flash.
 
If there are locked regions (as defined in the descriptor), then you will still need to unlock them by re-flashing a modified descriptor externally. However, flashrom can still flash to those regions which are not currently set to read-only.


At the time of writing, flashrom did not yet have a whitelist for the ThinkPad X200. If that is the case with your version of flashrom, you can use '''-p internal:laptop=force_I_want_a_brick'''.
Flashrom 1.0 or newer:
<pre>
flashrom -p internal -w coreboot.rom --ifd -i bios
</pre>


If you need the whitelist patch, apply this to the file board_enable.c then re-compile flashrom:
On older flashrom:
<pre>
flashrom -p internal -r old_coreboot.rom
ifdtool old_coreboot.rom -f layout
flashrom -p internal -w coreboot.rom -l layout -i bios
</pre>


[http://paste.debian.net/plain/141084 X200 flashrom whitelist]


=== Other flashrom patches (optional) ===
=== Other flashrom patches (optional) ===
Line 267: Line 305:


7WHT19WW corresponds to 1.06 running on x200t, which can be found out by just searching 7WHT19WW in search engine of choice
7WHT19WW corresponds to 1.06 running on x200t, which can be found out by just searching 7WHT19WW in search engine of choice
== Increase amount of preallocated ram for integrated graphics ==
The default amount of vram is set to 32MB. Some applications using the integrated graphic device can perform a lot better if this increased.
This is often the case for games and video decoding using VAAPI.
In order to change CMOS defaults, you will need '''nvramtool''':
<syntaxhighlight lang="bash" inline>cd util/nvramtool/
make
mv nvramtool ../../nvramtool
cd ../../
</syntaxhighlight>
The VGA shared RAM can be increased to 128MB, 256MB or 352MB by running as root:
<syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=128M</syntaxhighlight>
or
<syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=256M</syntaxhighlight>
or
<syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=352M</syntaxhighlight>
If you want this to be the default (fallback value if nvram is invalid) on your device:
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=128M</syntaxhighlight>
and flash that build/coreboot.rom
== Tips and trick (not necessarily coreboot related) ==
=== Recalibrate batteries ===
The EC (embedded controller) has the possibility to recalibrate batteries, the primary battery inside the laptop. To achieve this, plug the computer to AC and do the following to have the EC fully empty the battery:
First of all build ectool in util/ectool. If you want to calibrate the primary battery, run:
<syntaxhighlight lang="bash" inline>./ectool -w 0x23 -z 0x07</syntaxhighlight>
For the secondary battery (not present on this device, only on x301, t400, t500) execute:
<syntaxhighlight lang="bash" inline>./ectool -w 0x23 -z 0x08</syntaxhighlight>
Now wait a few hours while the battery fully discharges and charges back up.
[https://ticket.coreboot.org/issues/156 This could also be implemented in ACPI such that this can be achieved with the tpacpi-bat tools.]
=== Sensors mapping ===
{| class="wikitable"
!|sensor||X200||X200s||X200t
|-
|temp1
|colspan="3" style="text-align: center;" | CPU die
|-
|temp2
|colspan="3" style="text-align: center;" | Between mPCIe sockets
|-
|temp4
|colspan="3" style="text-align: center;" | CPU buck converter
|-
|temp5
|colspan="3" style="text-align: center;" | Battery¹
|-
|temp7
|colspan="3" style="text-align: center;" | Battery¹
|-
|temp9 ||SO-DIMM (other side of board)||?||ExpressCard
|-
|temp10² ||ExpressCard||?||SO-DIMM (other side of board)
|}
¹ Each battery seems to have different mapping on those. On X200T with 8 cell battery it seems to correspond to two 3-pin sensors on FETs, but 4 cell batteries only have one such sensor/fuse.
² On-die temperature sensor of MAX6694


== Research ==
== Research ==
* [[Board:lenovo/x200/internal_flashing_research| Research to get more details on the BIOS updates mecanism]]
* [[Board:lenovo/x200/internal_flashing_research| Research to get more details on the BIOS updates mecanism]]

Latest revision as of 15:31, 29 May 2018

Status

Thanks for your interest in Lenovo X200 port. Works:

  • USB
  • USB Debug (on the right port near the ThinkPad Logo)
  • Audio (internal speakers, internal mic, headphones, external mic)
  • WLAN (first minipcie slot)
  • WWAN (second minipcie slot)
  • UWB (third minipcie slot)
  • SD card slot
  • LAN
  • Battery and AC indicator
  • Thermal
  • EEPROM
  • Linux (through GRUB-as-payload)
  • trackpoint
  • keyboard
  • Bluetooth
  • LID
  • Video (internal panel and VGA)
  • Hotkeys
  • Fingerprint reader.
  • Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)
  • suspend to RAM (S3)
  • Expresscard slot (including hotplug)
  • Wake on LID, wake on Fn.
  • Dock
  • Digitizer on x200t variant
  • Modem

X200S and X200 Tablet

Both the X200S and X200 Tablet use a WSON-8 package for the flash chip. This has the same pinout as a SOIC-8 flash chip, but you will need to solder some (very thin) wires to a pin header since no clips are available for this type of connection.

Location on motherboard Here is an example

Regular X200 laptops will use either a SOIC-8 or SOIC-16 connection (recommended for average users, who most likely do not want to solder).

Proprietary components status

  • CPU microcode (optional) <see note 1>
  • VGA option rom (optional) => You need it if you want graphics in SeaBIOS but most payloads should work without it (text mode <see note 2> or corebootfb mode)
  • ME (Management Engine) (optional) => Can be removed by using a modified flash descriptor (see notes below about the ich9gen utility)
  • EC (Embedded Controller) => You do not have to touch it (just leave it where it is)

note 1:

VT-x (hardware-assisted virtualization) stops working without microcode updates. The laptop will randomly and sporadically crash without microcode updates. The conditions under which these crashes occur at currently not known.

Dumping the original firmware

First flashing needs to be external. phcoder used the buspirate and a pomona 5252 clip (SOIC-16). For SOIC-8 flash chips, you can use the Pomona 5250.

Unless modified (through the descriptor), the X200 flash as shipped by Lenovo is divided in 5 parts.

For systems with the 8MiB flash chip:

  • Descriptor (4K) - first region
  • ME (also includes AMT) (6100K) - 2nd region
  • Gbe (8K) - 3rd region
  • Platform (32K) - 4th region
  • BIOS (2M) - 5th region

For systems with the 4MiB flash chip:

  • Descriptor (4K) - first region
  • ME (no AMT) (2004K) - 2nd region
  • Gbe (8K) - 3rd region
  • Platform (32K) - 4th region
  • BIOS (2M) - 5th region

Flash chip sizes can be identified through flashrom. Generally, the following is true:

  • SOIC-8 = 4MiB (rare on these machines)
  • SOIC-16 = 8MiB (common on these machines)

The descriptor and ME regions are read-only. ME firmware is not readable.

All regions are re-writeable with an external SPI flasher, and the descriptor can be modified to unlock these regions (see notes about ich9gen below) for Host CPU / BIOS.

For coreboot we need to preserve at least the descriptor and Gbe regions while overwriting the flash chip contents. To achieve this there are 2 ways:

  • External flasher (most reliable method known at this time).
  • Unlock bootblock (method unknown at this time)

For the first method, proceed as follows:

  • Turn off your laptop
  • Remove the battery and AC adapter.
  • Remove the keyboard.
  • Connect your external SPI flasher to the SPI chip which is underneath the palmrest, around the position of the trackpoint under a protective layer.

Depending on the flasher that you use, you may need a separate +/- 3.3V DC power source (make sure not to feed any more than this). phcoder used the buspirate and for 3.3V DC he used an ATX PSU.

The pinout is as follows (colours are based on the buspirate): 

 ===  front (display) ====
 NC              -       - MISO (black)
 ground (brown)  -       - CS (white)
 NC              -       - NC
 NC              -       - NC
 NC              -       - NC
 NC              -       - NC
 MOSI (gray)     -       - +3.3V (red)
 violet (SCLK)   -       - NC
 ===  back (palmrest) ===

+3.3v (red) must ONLY be connected once the clip is connected, and make sure that the -3.3v is also connected beforehand.

NEVER connect +3.3v (red) prior to the other connections on your flash chip / programmer.

  • phcoder wasn't able to eliminate interference in his setup (you may have better luck), so it worked only on 30kHz; adding a battery increased the quality slightly. Read the flash twice, and compare (sha512sum) the files to be sure. Save a copy of the dump onto

external media. Due to interference it had to be read about 10 times, 2 of which were corrupted. 

flashrom -p <yourprogrammer> -r flash.bin
flashrom -p <yourprogrammer> -r flash2.bin
diff flash.bin flash2.bin

An alternative flashing guide (uses BeagleBone Black instead of Bus Pirate for faster, more reliable flashing) can be found at the libreboot website: Flashing the X200 with a BBB

See also In-System Programming

Flashing your coreboot ROM image

You cannot simply build the image and flash it, without first including several other "regions" that are discussed below.

The easiest way to handle the non-coreboot blobs that need to be present on flash is by using flashrom 1.0 or later.

With ME firmware updates/AMT

With flashrom 1.0 or later you don't need to extract any blob from the vendor image, you can just leave them where they are, which is highly recommended!

First of all make a backup with your external programmer and verify it be a proper image. 

flashrom -p "external_programmer" -r vendor.rom && flashrom -p "external_programmer" -v vendor.rom

After having successfully made a backup of you vendor firmware it is time to flash the coreboot image you build: 

flashrom -p "external_programmer" -w coreboot.rom --ifd --image bios --noverify-all

and done!

To update the coreboot image later on do the following: 

flashrom -p internal -w coreboot.rom --ifd --image bios

Without ME firmware updates/AMT

On this hardware it is possible to ommit the ME firmware updates while still using the Intel firmware descriptor + GBE region. This make it possible to use the flash region the ME used for bios region, allowing for much larger payloads (useful for Linux payloads). This requires the use a modified descriptor and moving things around a bit.

First of all make a backup with your external programmer and verify it be a proper image. 

flashrom -p "external_programmer" -r vendor.rom && flashrom -p "external_programmer" -v vendor.rom

There is a tool to generate a modified flash descriptor: 'blobtool' go to util/blobtool: 

make
./blobtool ifd-x200.spec ifd-x200.set ifd.bin

if your flash is not 8M modify ifd-x200.set e.g. 4M 

diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set
index 255eb88b70..25ae281906 100644
--- a/util/blobtool/ifd-x200.set
+++ b/util/blobtool/ifd-x200.set
@@ -35,7 +35,7 @@
        "flmap2_msl" = 0x1,
        "flmap2_reserved" = 0x0,
 
-       "flcomp_density1" = 0x4,
+       "flcomp_density1" = 0x3,
        "flcomp_density2" = 0x2,
        "flcomp_reserved0" = 0x0,
        "flcomp_reserved1" = 0x0,
@@ -56,7 +56,7 @@
        "flreg0_reserved1" = 0x0,
        "flreg1_base" = 0x3,
        "flreg1_reserved0" = 0x0,
-       "flreg1_limit" = 0x7ff,
+       "flreg1_limit" = 0x3ff,
        "flreg1_reserved1" = 0x0,
        "flreg2_base" = 0x1fff,
        "flreg2_reserved0" = 0x0,

or for 16M flash 

diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set
index 255eb88b70..bbcb159616 100644
--- a/util/blobtool/ifd-x200.set
+++ b/util/blobtool/ifd-x200.set
@@ -35,7 +35,7 @@
        "flmap2_msl" = 0x1,
        "flmap2_reserved" = 0x0,
 
-       "flcomp_density1" = 0x4,
+       "flcomp_density1" = 0x5,
        "flcomp_density2" = 0x2,
        "flcomp_reserved0" = 0x0,
        "flcomp_reserved1" = 0x0,
@@ -56,7 +56,7 @@
        "flreg0_reserved1" = 0x0,
        "flreg1_base" = 0x3,
        "flreg1_reserved0" = 0x0,
-       "flreg1_limit" = 0x7ff,
+       "flreg1_limit" = 0x1fff,
        "flreg1_reserved1" = 0x0,
        "flreg2_base" = 0x1fff,
        "flreg2_reserved0" = 0x0,

Now let's start by flashing this descriptor. It first needs some padding since as of writing flashrom still needs image that match the whole flash size even if only a region is flashed.

modify '8' in the command to create your flash by your flash size in MB. 

dd if=/dev/zero of=padding.bin bs=$((8 * 1024 * 1024 - 4096)) count=1
cat ifd.bin padding.bin > ifd_8M.bin
flashrom -p "external_programmer" -w ifd_8M.bin --ifd --image fd --noverify-all

Given that the GBE region is a different offset compared to vendor, we need to move it around too. First extract it from the vendor image: 

ifdtool vendor.rom -x

Now inject the GBE region into the previously created ifd_8M.bin and flash it to the SPI flash. 

ifdtool -i GBE:flashregion_3_gbe.bin ifd_8M.bin
flashrom -p "external_programmer" -w ifd_8M.bin.new --ifd --image gbe --noverify-all

Now finally we can flash our coreboot image. Notice that when building coreboot CONFIG_CBFS_SIZE can now be safely set to 0x7fd000 (8 * 1024 * 1024 - 4096 - 8192) for 8M flash to make a maximal use of the available flash: 

flashrom -p "external_programmer" -w coreboot.rom --ifd --image bios --noverify-all

On future coreboot updates (no need for external programmer now) simply never touch the other regions again: 

flashrom -p internal -w coreboot.rom --ifd --image bios

Internal flashing

Once coreboot is installed and running, internal flashing should be easier.

Either generate a layout using ifdtool to only flash the bios region, or use flashrom 1.0 or later to read the layout from the Firmware Descriptor on flash.

Flashrom 1.0 or newer: 

flashrom -p internal -w coreboot.rom --ifd -i bios

On older flashrom: 

flashrom -p internal -r old_coreboot.rom
ifdtool old_coreboot.rom -f layout
flashrom -p internal -w coreboot.rom -l layout -i bios


Other flashrom patches (optional)

Most X200 laptops use one of the Macronix flash chips. Those chips will be detected several times, forcing you to use the -c parameter for selecting a flash chip.

One easy and permanent way to avoid this is to remove those definitions that are redundant to you (this method is inappropriate for upstream).

Apply the following patch to flashchips.c: for purging redundant flash chip definitions

Thermal throttling adjustment

To adjust threshold of thermal throttling on x200 change critical temperatures of individual ThermalZones inside src/ec/lenovo/h8/acpi/thermal.asl.

C2K function stands for Celsius to Kelvin

Get version of EC firmware

To get firmware version of EC running on x200 running coreboot run

grep 'at EC' /proc/asound/cards

Sample output:

ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6

7WHT19WW corresponds to 1.06 running on x200t, which can be found out by just searching 7WHT19WW in search engine of choice

Increase amount of preallocated ram for integrated graphics

The default amount of vram is set to 32MB. Some applications using the integrated graphic device can perform a lot better if this increased. This is often the case for games and video decoding using VAAPI.

In order to change CMOS defaults, you will need nvramtool: <syntaxhighlight lang="bash" inline>cd util/nvramtool/ make mv nvramtool ../../nvramtool cd ../../ </syntaxhighlight>

The VGA shared RAM can be increased to 128MB, 256MB or 352MB by running as root:

<syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=128M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=256M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -w gfx_uma_size=352M</syntaxhighlight>

If you want this to be the default (fallback value if nvram is invalid) on your device: <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=128M</syntaxhighlight> and flash that build/coreboot.rom

Tips and trick (not necessarily coreboot related)

Recalibrate batteries

The EC (embedded controller) has the possibility to recalibrate batteries, the primary battery inside the laptop. To achieve this, plug the computer to AC and do the following to have the EC fully empty the battery: First of all build ectool in util/ectool. If you want to calibrate the primary battery, run: <syntaxhighlight lang="bash" inline>./ectool -w 0x23 -z 0x07</syntaxhighlight> For the secondary battery (not present on this device, only on x301, t400, t500) execute: <syntaxhighlight lang="bash" inline>./ectool -w 0x23 -z 0x08</syntaxhighlight> Now wait a few hours while the battery fully discharges and charges back up.

This could also be implemented in ACPI such that this can be achieved with the tpacpi-bat tools.

Sensors mapping

sensor X200 X200s X200t
temp1 CPU die
temp2 Between mPCIe sockets
temp4 CPU buck converter
temp5 Battery¹
temp7 Battery¹
temp9 SO-DIMM (other side of board) ? ExpressCard
temp10² ExpressCard ? SO-DIMM (other side of board)

¹ Each battery seems to have different mapping on those. On X200T with 8 cell battery it seems to correspond to two 3-pin sensors on FETs, but 4 cell batteries only have one such sensor/fuse.

² On-die temperature sensor of MAX6694

Research

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