JTAG/BSDL Guide: Difference between revisions
(just more verbage) |
No edit summary |
||
| (6 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
= | == What is JTAG? == | ||
[http://en.wikipedia.org/wiki/Jtag JTAG] is an IEEE standard that has been adopted to provide a consistant way of programming and debugging chips. JTAG is supported by a large number of chips and manufacturers. They include: | |||
JTAG is an IEEE standard that has been adopted to provide a consistant way of programming and debugging chips. JTAG is supported | |||
* Many embedded PowerPC chips | * Many embedded PowerPC chips | ||
| Line 12: | Line 8: | ||
* Most FPGA's | * Most FPGA's | ||
Using chips that support JTAG decreases software development time and decreases the costs of doing development. Chips that do not have JTAG support usually require expensive hardware to configure and debug them | Using chips that support JTAG decreases software development time and decreases the costs of doing development. Chips that do not have JTAG support usually require expensive hardware to configure and debug them (thousands to tens of thousands of dollars). This is prohibitive to most Linux developers. | ||
JTAG ports are still very uncommon on x86 hardware. However, most hardware designs are moving in that direction so future x86 chips will probably also have JTAG ports. AMD's Geode GX2 systems are an example of x86 systems with JTAG support. | |||
= | == FAQ == | ||
=== Why JTAG? === | |||
If you are designing a new hardware and you are interested in supporting coreboot, you should make a JTAG port available and select chips which allow programming via JTAG. While this is not yet possible for higher end x86 chips, it is often possible for embedded designs. | |||
=== How can I connect to a JTAG port from Linux? === | |||
= | For less than $20 you can buy a parallel to JTAG cable and be on your way. Once you have an adapter, you can use the jtag program that is part of the [http://openwince.sourceforge.net/ openwince sourceforge project]. | ||
=== I have the cable, now I can't talk to my chip === | |||
The jtag program is still under development; lots of chips are not supported yet. Don't worry, you can add support for it. You need to find the corresponding BSDL file for the chip. Chip manufacturers provide BSDL files on their websites. | The jtag program is still under development; lots of chips are not supported yet. Don't worry, you can add support for it. You need to find the corresponding BSDL file for the chip. Chip manufacturers provide BSDL files on their websites. | ||
= | === OK, I can see my chip over JTAG. Now what? === | ||
That depends on the chip. Some chips will let you program them, some CPU's will let you single step instructions and do debugging. It depends on the chip and the manufacturer. CPU's that support single stepping make BIOS development particularly easy. | That depends on the chip. Some chips will let you program them, some CPU's will let you single step instructions and do debugging. It depends on the chip and the manufacturer. CPU's that support single stepping make BIOS development particularly easy. | ||
= | === Darn, my board doesn't have a JTAG port! === | ||
= | === Darn, my chips don't work with JTAG! === | ||
Well, that's what being a smart consumer is about :) In general, don't buy hardware that isn't Linux friendly. | Well, that's what being a smart consumer is about :) In general, don't buy hardware that isn't Linux friendly. | ||
= ' | == A sample session == | ||
Here is a sample session using the GPL'd jtag tool from within a bash shell when scanning the JTAG bus that has a Xilinx Spartan-3 FPGA & and Xilinx CPLD on it. | |||
jtag> cable parallel 0x378 DLC5 | |||
Initializing Xilinx DLC5 JTAG Parallel Cable III on parallel port at 0x378 | |||
jtag> detect | |||
IR length: 14 | |||
Chain length: 2 | |||
Device Id: 00000101000001000110000010010011 | |||
Manufacturer: Xilinx | |||
Unknown part! | |||
Device Id: 00010001010000101000000010010011 | |||
Manufacturer: Xilinx | |||
Part: xc3s1000_ft256 | |||
Stepping: 0 | |||
Filename: /usr/share/jtag/xilinx/xc3s1000_ft256/xc3s1000_ft256 | |||
chain.c(110) Part 0 without active instruction | |||
chain.c(133) Part 0 without active instruction | |||
chain.c(110) Part 0 without active instruction | |||
jtag> instruction SAMPLE/PRELOAD | |||
jtag> shift ir | |||
chain.c(110) Part 0 without active instruction | |||
jtag> | |||
== External JTAG Links == | |||
* [http://www.intel.com/design/flcomp/applnots/29218602.PDF Intel's JTAG Guide] | * [http://www.intel.com/design/flcomp/applnots/29218602.PDF Intel's JTAG Guide] | ||
| Line 41: | Line 66: | ||
* [http://www.jtag.com/main.php jtag.com] | * [http://www.jtag.com/main.php jtag.com] | ||
* [http://openwince.sourceforge.net/jtag/ Jtag tools for Linux] | * [http://openwince.sourceforge.net/jtag/ Jtag tools for Linux] | ||
* [http://packages.debian.org/testing/embedded/openwince-jtag JTAG tools packaged for | * [http://packages.debian.org/testing/embedded/openwince-jtag JTAG tools packaged for Debian] | ||
* [http://www.arium.com/products/ecm50ice.html Arium ECM-50 (Intel JTAG/ITL hardware debugger)] | * [http://www.arium.com/products/ecm50ice.html Arium ECM-50 (Intel JTAG/ITL hardware debugger)] | ||
* [http://wiki.openwrt.org/OpenWrtDocs/Customizing/Hardware/JTAG_Cable Different JTAG cables and software] | |||
Latest revision as of 13:04, 15 January 2008
What is JTAG?
JTAG is an IEEE standard that has been adopted to provide a consistant way of programming and debugging chips. JTAG is supported by a large number of chips and manufacturers. They include:
- Many embedded PowerPC chips
- Most ARM chips
- Many flash chips
- Most FPGA's
Using chips that support JTAG decreases software development time and decreases the costs of doing development. Chips that do not have JTAG support usually require expensive hardware to configure and debug them (thousands to tens of thousands of dollars). This is prohibitive to most Linux developers.
JTAG ports are still very uncommon on x86 hardware. However, most hardware designs are moving in that direction so future x86 chips will probably also have JTAG ports. AMD's Geode GX2 systems are an example of x86 systems with JTAG support.
FAQ
Why JTAG?
If you are designing a new hardware and you are interested in supporting coreboot, you should make a JTAG port available and select chips which allow programming via JTAG. While this is not yet possible for higher end x86 chips, it is often possible for embedded designs.
How can I connect to a JTAG port from Linux?
For less than $20 you can buy a parallel to JTAG cable and be on your way. Once you have an adapter, you can use the jtag program that is part of the openwince sourceforge project.
I have the cable, now I can't talk to my chip
The jtag program is still under development; lots of chips are not supported yet. Don't worry, you can add support for it. You need to find the corresponding BSDL file for the chip. Chip manufacturers provide BSDL files on their websites.
OK, I can see my chip over JTAG. Now what?
That depends on the chip. Some chips will let you program them, some CPU's will let you single step instructions and do debugging. It depends on the chip and the manufacturer. CPU's that support single stepping make BIOS development particularly easy.
Darn, my board doesn't have a JTAG port!
Darn, my chips don't work with JTAG!
Well, that's what being a smart consumer is about :) In general, don't buy hardware that isn't Linux friendly.
A sample session
Here is a sample session using the GPL'd jtag tool from within a bash shell when scanning the JTAG bus that has a Xilinx Spartan-3 FPGA & and Xilinx CPLD on it.
jtag> cable parallel 0x378 DLC5 Initializing Xilinx DLC5 JTAG Parallel Cable III on parallel port at 0x378 jtag> detect IR length: 14 Chain length: 2 Device Id: 00000101000001000110000010010011 Manufacturer: Xilinx Unknown part! Device Id: 00010001010000101000000010010011 Manufacturer: Xilinx Part: xc3s1000_ft256 Stepping: 0 Filename: /usr/share/jtag/xilinx/xc3s1000_ft256/xc3s1000_ft256 chain.c(110) Part 0 without active instruction chain.c(133) Part 0 without active instruction chain.c(110) Part 0 without active instruction jtag> instruction SAMPLE/PRELOAD jtag> shift ir chain.c(110) Part 0 without active instruction jtag>