Nvidia CK804 Porting Notes: Difference between revisions

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This document does not (at present) attempt to be as complete as the [[AMD_Geode_Porting_Guide]], which has more general information.
This document does not (at present) attempt to be as complete as the [[AMD Geode Porting Guide]], which has more general information.


== Documentation ==
== Documentation ==
There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.
There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.


== Audio and Network ==
== Audio and Network ==


If your CK804 has an AC97 codec, or ethernet PHY connected to it,
If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define '''CK804_USE_ACI''' and '''CK804_USE_NIC''' respectively.
you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.


Without CK804_USE_ACI=1, the audio driver
Without '''CK804_USE_ACI = 1''', the audio driver will time out when attempting to communicate with the codec.
will time out when attempting to communicate with the codec.


== Interrupt Routing Registers ==
== Interrupt Routing Registers ==
Obtained via playing with these registers with setpci(8).
Some information is still missing.


This table maps nibble values of these registers to APIC pin numbers.
Please note that this is valid for [[Nvidia MCP55 Porting Notes|MCP55]] too.


These registers are in the LPC bridge configuration space.
Obtained via playing with these registers with '''setpci(8)'''. Some information is still missing.


{| border="1" class="wikitable"
These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).
|+ nibble values for routing registers
 
! nibble !! pin
'''Nibble values for routing registers:'''
|-
 
{| border="0" style="font-size: smaller"
|- bgcolor="#6699ff"
! align="left" | Nibble
! align="left" | APIC Pin
|- bgcolor="#eeeeee"
| 1h || 23
| 1h || 23
|-
|- bgcolor="#dddddd"
| 2h || 22?
| 2h || 22
|-
|- bgcolor="#eeeeee"
| 3h || 16
|- bgcolor="#dddddd"
| 4h || 17
|- bgcolor="#eeeeee"
| 5h || 5
|- bgcolor="#dddddd"
| 6h || 18
|- bgcolor="#eeeeee"
| 7h || 7
|- bgcolor="#dddddd"
| 8h || 20
| 8h || 20
|-
|- bgcolor="#dddddd"
| Ch || 12
| Ch || 12
|-
|- bgcolor="#eeeeee"
| Dh || 21
| Dh || 21
|-
|- bgcolor="#dddddd"
| Eh || 14
| Eh || 14
|-
|- bgcolor="#eeeeee"
| Fh || 15
| Fh || 15
|}
|}


{| border="1" class="wikitable"
'''7c.l:'''
|+ 7c.l
 
! bits !! description
{| border="0" style="font-size: smaller"
|-
|- bgcolor="#6699ff"
! align="left" | Bits
! align="left" | Description
|- bgcolor="#eeeeee"
| 27:24 || SATA at device 7, second port
| 27:24 || SATA at device 7, second port
|-
|- bgcolor="#dddddd"
| 23:20 || SATA at device 8, second port
| 23:20 || SATA at device 8, second port
|-
|- bgcolor="#eeeeee"
| 15:0 || PCI IRQ mappings?
| 15:0 || PCI IRQ mappings?
|}
|}


{| border="1" class="wikitable"
'''80.l:'''
|+ 80.l
 
! bits !! description
{| border="0" style="font-size: smaller"
|-
|- bgcolor="#6699ff"
! align="left" | Bits
! align="left" | Description
|- bgcolor="#eeeeee"
| 31:28 || SATA at device 7, first port
| 31:28 || SATA at device 7, first port
|-
|- bgcolor="#dddddd"
| 27:24 || SATA at device 8, first port
| 27:24 || SATA at device 8, first port
|-
|- bgcolor="#eeeeee"
| 15:12 || EHCI (device 2, function 1)
| 15:12 || EHCI (device 2, function 1)
|}
|}


{| border="1" class="wikitable"
'''84.l:'''
|+ 84.l
 
! bits !! description
{| border="0" style="font-size: smaller"
|-
|- bgcolor="#6699ff"
! align="left" | Bits
! align="left" | Description
|- bgcolor="#eeeeee"
| 19:16 || AC'97 audio (device 4, function 0)
|- bgcolor="#eeeeee"
| 11:8 || NIC (device 10, function 0)
| 11:8 || NIC (device 10, function 0)
|-
|- bgcolor="#dddddd"
| 3:0 || OHCI (device 2, function 0)
| 3:0 || OHCI (device 2, function 0)
|}
|}
One thing to note is that interrupts on both ports of the SATA controllers
should be routed to the same pin so that the device behaves the way the
driver expects them to.
{{Cc-by-2.5}}

Latest revision as of 14:11, 3 February 2010

This document does not (at present) attempt to be as complete as the AMD Geode Porting Guide, which has more general information.

Documentation

There is no publicly available documentation on the CK804, the source (and, of course, reverse engineering) is your only hope.

Audio and Network

If your CK804 has an AC97 codec, or ethernet PHY connected to it, you'll probably want to define CK804_USE_ACI and CK804_USE_NIC respectively.

Without CK804_USE_ACI = 1, the audio driver will time out when attempting to communicate with the codec.

Interrupt Routing Registers

Please note that this is valid for MCP55 too.

Obtained via playing with these registers with setpci(8). Some information is still missing.

These routing registers are in the LPC bridge PCI configuration space (device 1, function 0).

Nibble values for routing registers:

Nibble APIC Pin
1h 23
2h 22
3h 16
4h 17
5h 5
6h 18
7h 7
8h 20
Ch 12
Dh 21
Eh 14
Fh 15

7c.l:

Bits Description
27:24 SATA at device 7, second port
23:20 SATA at device 8, second port
15:0 PCI IRQ mappings?

80.l:

Bits Description
31:28 SATA at device 7, first port
27:24 SATA at device 8, first port
15:12 EHCI (device 2, function 1)

84.l:

Bits Description
19:16 AC'97 audio (device 4, function 0)
11:8 NIC (device 10, function 0)
3:0 OHCI (device 2, function 0)

One thing to note is that interrupts on both ports of the SATA controllers should be routed to the same pin so that the device behaves the way the driver expects them to.


Creative Commons License
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