Developer Manual/RAM init: Difference between revisions
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=== Introduction === | |||
One of the most important tasks of coreboot is to '''initialize your system RAM'''. | One of the most important tasks of coreboot is to '''initialize your system RAM'''. | ||
This initialization depends on the type of RAM in your motherboard. To detect the type of RAM the | This initialization depends on the type of RAM in your motherboard. To detect the type of RAM the | ||
SPD (Serial Presence Detect) must be read for each DIMM. This reading is done using I2C communication using one of the [[I2C]] buses on the motherboard. The exact method of reading depends on the motherboard. | SPD (Serial Presence Detect) must be read for each DIMM. This reading is done using I2C communication using one of the [[Developer Manual/I2C]] buses on the motherboard. The exact method of reading depends on the motherboard. | ||
Coreboot supports two methods to initialize your RAM: | |||
* native RAM init | |||
* using the MRC blob | |||
=== Main Goals === | |||
* Use highest clock-rate supported by the board and every DIMM installed | |||
* Find common settings like CAS Latency | |||
* Calibrate delay units, impedance and driver strength | |||
=== SDRAM === | === SDRAM === | ||
| Line 22: | Line 32: | ||
=== DDR === | === DDR === | ||
Duties: | |||
* Configure extended mode register | |||
* Configure load mode register | |||
=== DDR2 === | === DDR2 === | ||
Duties: | |||
* program Mode Registers and Extended Mode Registers | |||
* calibrate On-Die-Termination resistors | |||
* set output drive levels | |||
* find working command rate (1T or 2T) | |||
=== DDR3 === | === DDR3 === | ||
To easy PCB design the fly-by topology has been adopted. It requires additional measurements and calibration in comparison to DDR2. | |||
Duties: | |||
* program Mode Registers and Extended Mode Registers | |||
* calibrate On-Die-Termination resistors and dynamic On-Die-Termination resistors | |||
* compensate delay between DQS and DQ signals | |||
* compensate delay between CMD and DQ signals | |||
* find working command rate (1T or 2T) | |||
* set output driver strength | |||
=== Resources === | === Resources === | ||
* http://www.rampedia.org/ | |||
SDRAM: | SDRAM: | ||
Latest revision as of 07:24, 12 October 2015
Introduction
One of the most important tasks of coreboot is to initialize your system RAM.
This initialization depends on the type of RAM in your motherboard. To detect the type of RAM the SPD (Serial Presence Detect) must be read for each DIMM. This reading is done using I2C communication using one of the Developer Manual/I2C buses on the motherboard. The exact method of reading depends on the motherboard.
Coreboot supports two methods to initialize your RAM:
- native RAM init
- using the MRC blob
Main Goals
- Use highest clock-rate supported by the board and every DIMM installed
- Find common settings like CAS Latency
- Calibrate delay units, impedance and driver strength
SDRAM
There are a number of steps you have to perform to properly initialize SDRAM. This depends on the chipset, as well as the DIMMs which are inserted into the mainboard (and their properties, such as CAS latencies, and so on).
Sample northbridge datasheets:
- http://support.intel.com/design/chipsets/810/
- http://support.intel.com/design/chipsets/datashts/290656.htm
- http://download.intel.com/design/chipsets/datashts/29065602.pdf
- http://www.intel.com/Assets/PDF/datasheet/307502.pdf
- http://www.intel.com/assets/pdf/datasheet/318463.pdf
Sample SDRAM datasheets:
- http://www.micron.com/products/partdetail?part=MT48LC16M16A2BG-75
- http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
DDR
Duties:
- Configure extended mode register
- Configure load mode register
DDR2
Duties:
- program Mode Registers and Extended Mode Registers
- calibrate On-Die-Termination resistors
- set output drive levels
- find working command rate (1T or 2T)
DDR3
To easy PCB design the fly-by topology has been adopted. It requires additional measurements and calibration in comparison to DDR2.
Duties:
- program Mode Registers and Extended Mode Registers
- calibrate On-Die-Termination resistors and dynamic On-Die-Termination resistors
- compensate delay between DQS and DQ signals
- compensate delay between CMD and DQ signals
- find working command rate (1T or 2T)
- set output driver strength
Resources
SDRAM:
- Intel SPD Standard
- Micron 512 MB SDRAM Datasheet (PDF) -- contains some helpful explanations
DDR SDRAM:
- JEDEC DDR SPD Standard (PDF)
- Understanding DDR Serial Presence Detect (SPD) Table
- Micron DDR400 Datasheet
DDR2 SDRAM
- JEDEC DDR2 Standard (PDF)
- DDR2 DIMM SPD Definition
- Micron DDR2 Datasheets: 512MB-2GB 512MB-4GB
DDR3 SDRAM
Note: Micron lists SPD values for all the memory they produce. This really helps when trying to trouble shoot memory and SPD values. Micron SPD Lookup.