Board:gigabyte/ga-g41m-es2l: Difference between revisions
(30 intermediate revisions by 2 users not shown) | |||
Line 33: | Line 33: | ||
Finally return to the coreboot root directory: | Finally return to the coreboot root directory: | ||
<syntaxhighlight lang="bash" inline>cd ../../../../</syntaxhighlight> | <syntaxhighlight lang="bash" inline>cd ../../../../</syntaxhighlight> | ||
Line 45: | Line 44: | ||
CONFIG_USE_OPTION_TABLE=y | CONFIG_USE_OPTION_TABLE=y | ||
In case you do not want CPU microcode updates included in your ROM, add this line: | In case you '''do not''' want CPU microcode updates included in your ROM, add this line: | ||
CONFIG_CPU_MICROCODE_CBFS_NONE=y | CONFIG_CPU_MICROCODE_CBFS_NONE=y | ||
In case you do want to include CPU microcode updates in your ROM, add these lines: | In case you '''do''' want to include CPU microcode updates in your ROM, add these lines: | ||
CONFIG_USE_BLOBS=y | CONFIG_USE_BLOBS=y | ||
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y | CONFIG_CPU_MICROCODE_CBFS_GENERATE=y | ||
Line 68: | Line 67: | ||
Navigate to '''Devices''' and make sure that ''Use native graphics initialization'' is ''enabled'' [*]. | Navigate to '''Devices''' and make sure that ''Use native graphics initialization'' is ''enabled'' [*]. | ||
Navigate to '''Generic Drivers''' and set your ethernet MAC address in ''Realtek rt8168 mac address''. | Navigate to '''Generic Drivers''' and set your ethernet MAC address in ''Realtek rt8168 mac address''. | ||
* You can retrieve | * You can retrieve your MAC address either from your OS when running the vendor BIOS (with ''ifconfig -a'' for instance), or from the white label on the ethernet port. | ||
Navigate to '''Payload''' and set your | Navigate to '''Payload''' and set your SeaBIOS configuration in ''SeaBIOS config file''. | ||
* This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ''~/Downloads/coreboot/.seabiosconfig'' | * This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ''~/Downloads/coreboot/.seabiosconfig'' | ||
Line 84: | Line 81: | ||
Now build your ROM: | Now build your ROM: | ||
<syntaxhighlight lang="bash" inline>make</syntaxhighlight> | <syntaxhighlight lang="bash" inline>make</syntaxhighlight> | ||
== CMOS default values == | |||
By default, the VGA shared RAM on this board is set to 64MB, and the ''power on after fail'' option is enabled. While this is fine for server use, this is not ideal for desktop or HTPC use. | |||
In order to change CMOS defaults, you will need '''nvramtool''': | |||
<syntaxhighlight lang="bash" inline>cd util/nvramtool/ | |||
make | |||
mv nvramtool ../../nvramtool | |||
cd ../../ | |||
</syntaxhighlight> | |||
Power on after fail can be disabled by running: | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w power_on_after_fail=Disable</syntaxhighlight> | |||
The VGA shared RAM can be increased to 128MB, 256MB or 352MB by running: | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=128M</syntaxhighlight> | |||
or | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=256M</syntaxhighlight> | |||
or | |||
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=352M</syntaxhighlight> | |||
== Backing up the vendor BIOS == | |||
This board can be flashed from the vendor BIOS with flashrom, which is in the repositories of nearly every GNU/Linux distribution. | |||
It has two chips, which is supported by flashrom's ''dualbiosindex'' option. '''It is recommended to use at least flashrom 0.9.7 because support for this feature is buggy in older releases.''' | |||
To make a backup of the main BIOS chip, run: | |||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom</syntaxhighlight> | |||
To make a backup of the backup BIOS chip, run: | |||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom</syntaxhighlight> | |||
== Internal flashing == | == Internal flashing == | ||
As coreboot does not support Gigabyte's DualBIOS feature, only the '''M_BIOS chip''' has to be flashed. The '''B_BIOS''' chip can safely be erased. | |||
To erase the backup BIOS chip, run: | |||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=1 -E</syntaxhighlight> | |||
To flash the main BIOS chip, | To flash the main BIOS chip, run: | ||
<syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom</syntaxhighlight> | |||
== External flashing == | == External flashing == | ||
This board | This board is rather hard to flash, because powering the Vcc pin on the flash chip also powers the southbridge, causing a voltage drop likely resulting in errors reading, writing and verifying the chip. | ||
It has been found that this can be worked around by powering up the board normally (even if it doesn't boot) and then shutting it down by holding the power button for 5 seconds (or by shorting the according pins). Then connect your SPI flasher (Vcc too!) and proceed as usual. | |||
As stated above: only M_BIOS has to be flashed. B_BIOS can simply be erased. (Or flashed as well, but that won't make a difference.) | As stated above: only '''M_BIOS''' has to be flashed. '''B_BIOS''' can simply be erased. (Or flashed as well, but that won't make a difference.) | ||
== Chip pinout == | == Chip pinout == | ||
Line 112: | Line 143: | ||
-gnd mosi- | o | | -gnd mosi- | o | | ||
_______________ -cs--miso---gnd- | _______________ -cs--miso---gnd- | ||
== Status (as of commit 5360c7ef94) == | == Status (as of commit 5360c7ef94) == | ||
Line 117: | Line 149: | ||
|CPU_status = OK | |CPU_status = OK | ||
|CPU_comments = Core 2 Quad up to 1333MHz FSB. Modded LGA771 Xeons included. | |CPU_comments = Core 2 Duo/Quad up to 1333MHz FSB. Modded LGA771 Xeons included. Pentium 4/D won't boot. | ||
|CPU_L1_status = OK | |CPU_L1_status = OK | ||
|CPU_L2_status = OK | |CPU_L2_status = OK | ||
Line 132: | Line 164: | ||
|RAM_DDR2_comments = PC2-5300 CAS 5, PC2-6400 CAS 6 and PC2-6400 CAS 5 tested. | |RAM_DDR2_comments = PC2-5300 CAS 5, PC2-6400 CAS 6 and PC2-6400 CAS 5 tested. | ||
|RAM_DDR3_status = N/A | |RAM_DDR3_status = N/A | ||
|RAM_dualchannel_status = | |RAM_dualchannel_status = OK | ||
|RAM_ecc_status = N/A | |RAM_ecc_status = N/A | ||
|IDE_status = | |IDE_status = OK | ||
|IDE_comment = https://review.coreboot.org/#/c/19627/ | |||
|IDE_25_status = Untested | |IDE_25_status = Untested | ||
|SATA_status = OK | |SATA_status = OK | ||
Line 158: | Line 191: | ||
|AGP_cards_status = N/A | |AGP_cards_status = N/A | ||
|PCIE_cards_status = N/A | |PCIE_cards_status = N/A | ||
|PCIE_x1_status = | |PCIE_x1_status = Untested | ||
|PCIE_x2_status = N/A | |PCIE_x2_status = N/A | ||
|PCIE_x4_status = N/A | |PCIE_x4_status = N/A | ||
|PCIE_x8_status = N/A | |PCIE_x8_status = N/A | ||
|PCIE_x16_status = | |PCIE_x16_status = OK | ||
|PCIE_x16_comments = SDVO/ADD2 cards work fine | |PCIE_x16_comments = SDVO/ADD2 cards also work fine. | ||
|PCIE_x32_status = N/A | |PCIE_x32_status = N/A | ||
|HTX_status = N/A | |HTX_status = N/A | ||
Line 175: | Line 208: | ||
|Game_port_status = N/A | |Game_port_status = N/A | ||
|IR_status = N/A | |IR_status = N/A | ||
|Speaker_status = | |Speaker_status = OK | ||
|DiskOnChip_status = N/A | |DiskOnChip_status = N/A | ||
Line 183: | Line 216: | ||
|CAN_bus_status = N/A | |CAN_bus_status = N/A | ||
|CPUfreq_status = OK | |CPUfreq_status = OK | ||
|Powersave_status = | |Powersave_status = N/A | ||
|ACPI_status = OK | |ACPI_status = OK | ||
|SMBus_status = OK | |SMBus_status = OK |
Latest revision as of 16:00, 9 May 2017
This page describes how to use coreboot on the Gigabyte ga-g41m-es2l mainboard.
SeaBIOS ATA DMA
By default, SeaBIOS uses PIO mode for ATA interfaces. On the ICH7 southbridge, this is very slow. Loading a kernel + initramfs can take up to 20 seconds on this board.
When using ATA DMA mode, this bug disappears. This will have to be set explicitly in the SeaBIOS config file, and selected from coreboot's menuconfig.
From the coreboot root directory, go to payloads/external/SeaBIOS/seabios: <syntaxhighlight lang="bash" inline>cd payloads/external/SeaBIOS/seabios/</syntaxhighlight>
Create a file called .config and add these lines to it:
CONFIG_COREBOOT=y CONFIG_ATA_DMA=y CONFIG_VGA_COREBOOT=y
Then, create a full .config file by running: <syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight>
Navigate to General Features and make sure the Build Target is set to Build for coreboot.
Navigate to Hardware support and make sure that ATA DMA is enabled [*].
Navigate to VGA ROM and make sure that VGA Hardware Type is set to coreboot linear framebuffer.
Exit menuconfig and save the changes.
It is probably easiest to move the .config file to the coreboot root directory, under a different name (e.g. .seabiosconfig), as coreboot already has its own .config file.
<syntaxhighlight lang="bash" inline>mv .config ../../../../.seabiosconfig</syntaxhighlight>
Finally return to the coreboot root directory: <syntaxhighlight lang="bash" inline>cd ../../../../</syntaxhighlight>
coreboot configuration
Create a file called .config and add at least these lines to it:
CONFIG_VENDOR_GIGABYTE=y CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_USE_OPTION_TABLE=y
In case you do not want CPU microcode updates included in your ROM, add this line:
CONFIG_CPU_MICROCODE_CBFS_NONE=y
In case you do want to include CPU microcode updates in your ROM, add these lines:
CONFIG_USE_BLOBS=y CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
By default, serial debugging output is enabled. It is very useful for debugging, but also slows down the boot process a lot. If you don't need serial debug or have no idea how to use it, disable it:
CONFIG_CONSOLE_SERIAL=n
Then, create a full .config file by running: <syntaxhighlight lang="bash" inline>make menuconfig</syntaxhighlight>
Navigate to General setup and make sure that Use CMOS for configuration values is enabled [*].
Navigate to Mainboard and make sure the Mainboard vendor is set to GIGABYTE and the Mainboard model to GA-G41M-ES2L.
Navigate to Chipset and make sure that Include CPU microcode in CBFS is set to either Generate from tree or Do not include microcode updates.
- In case you selected Generate from tree, make sure that General setup -> Allow use of binary-only repository is enabled [*].
Navigate to Devices and make sure that Use native graphics initialization is enabled [*].
Navigate to Generic Drivers and set your ethernet MAC address in Realtek rt8168 mac address.
- You can retrieve your MAC address either from your OS when running the vendor BIOS (with ifconfig -a for instance), or from the white label on the ethernet port.
Navigate to Payload and set your SeaBIOS configuration in SeaBIOS config file.
- This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ~/Downloads/coreboot/.seabiosconfig
Exit menuconfig and save the changes.
Now build your ROM:
<syntaxhighlight lang="bash" inline>make</syntaxhighlight>
CMOS default values
By default, the VGA shared RAM on this board is set to 64MB, and the power on after fail option is enabled. While this is fine for server use, this is not ideal for desktop or HTPC use.
In order to change CMOS defaults, you will need nvramtool: <syntaxhighlight lang="bash" inline>cd util/nvramtool/ make mv nvramtool ../../nvramtool cd ../../ </syntaxhighlight>
Power on after fail can be disabled by running: <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w power_on_after_fail=Disable</syntaxhighlight>
The VGA shared RAM can be increased to 128MB, 256MB or 352MB by running:
<syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=128M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=256M</syntaxhighlight> or <syntaxhighlight lang="bash" inline>./nvramtool -C build/coreboot.rom -w gfx_uma_size=352M</syntaxhighlight>
Backing up the vendor BIOS
This board can be flashed from the vendor BIOS with flashrom, which is in the repositories of nearly every GNU/Linux distribution.
It has two chips, which is supported by flashrom's dualbiosindex option. It is recommended to use at least flashrom 0.9.7 because support for this feature is buggy in older releases.
To make a backup of the main BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom</syntaxhighlight>
To make a backup of the backup BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom</syntaxhighlight>
Internal flashing
As coreboot does not support Gigabyte's DualBIOS feature, only the M_BIOS chip has to be flashed. The B_BIOS chip can safely be erased.
To erase the backup BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=1 -E</syntaxhighlight>
To flash the main BIOS chip, run: <syntaxhighlight lang="bash" inline>sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom</syntaxhighlight>
External flashing
This board is rather hard to flash, because powering the Vcc pin on the flash chip also powers the southbridge, causing a voltage drop likely resulting in errors reading, writing and verifying the chip.
It has been found that this can be worked around by powering up the board normally (even if it doesn't boot) and then shutting it down by holding the power button for 5 seconds (or by shorting the according pins). Then connect your SPI flasher (Vcc too!) and proceed as usual.
As stated above: only M_BIOS has to be flashed. B_BIOS can simply be erased. (Or flashed as well, but that won't make a difference.)
Chip pinout
B_BIOS M_BIOS _______________ -cs o vcc- -vcc---clk-mosi- -miso - | | - clk- | | -gnd mosi- | o | _______________ -cs--miso---gnd-
Status (as of commit 5360c7ef94)
Device/functionality | Status | Comments | ||||||
---|---|---|---|---|---|---|---|---|
CPU | ||||||||
CPU works | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Core 2 Duo/Quad up to 1333MHz FSB. Modded LGA771 Xeons included. Pentium 4/D won't boot. | ||||||
L1 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L2 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L3 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multiple CPU support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multi-core support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Hardware virtualization | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
RAM | ||||||||
EDO | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SDRAM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SO-DIMM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR2 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | PC2-5300 CAS 5, PC2-6400 CAS 6 and PC2-6400 CAS 5 tested. | ||||||
DDR3 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Dual channel support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
ECC support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Hardware | ||||||||
On-board IDE 3.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board IDE 2.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
On-board SATA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board SCSI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Ethernet | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Requires file in CBFS to keep the proper MAC address. | ||||||
On-board Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Modem | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board FireWire | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Smartcard reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board CompactFlash | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board PCMCIA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Wifi | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Bluetooth | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board SD card reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Add-on slots/cards | ||||||||
ISA add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Audio/Modem-Riser (AMR/CNR) cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Mini-PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Mini-PCI-Express add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
PCI-X add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
AGP graphics cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x1 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
PCI Express x2 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x4 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x8 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x16 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | SDVO/ADD2 cards also work fine. | ||||||
PCI Express x32 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
HTX add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Legacy / Super I/O | ||||||||
Floppy | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
Serial port 1 (COM1) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Serial port 2 (COM2) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Parallel port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
PS/2 keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
PS/2 mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
Game port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Infrared | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PC speaker | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
DiskOnChip | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Input | ||||||||
Trackpoint | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Touchpad | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fn Hotkeys | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fingerprint Reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Laptop | ||||||||
Docking VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Displayport | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Thinklight | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Webcam | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Miscellaneous | ||||||||
Sensors / fan control | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Fan speed seems fixed. In practice, this is not a problem. | ||||||
Hardware watchdog | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
SMBus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
CAN bus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
CPU frequency scaling | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Other powersaving features | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
ACPI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Reboot | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Poweroff | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Suspend | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Nonstandard LEDs | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
High precision event timers (HPET) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Random number generator (RNG) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Wake on modem ring | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Wake on LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Wake on keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Wake on mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
TPM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Flashrom | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Can be flashed from vendor BIOS, with -p internal:dualbiosindex=0/1. Chip 1 can safely be erased with -E. |