Console and outputs: Difference between revisions
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* A supported dongle: | * A supported dongle: | ||
** A GNU/Linux computer with usb peripheral or OTG and the g_dbpg driver. Single Board computers typically have that. | ** A GNU/Linux computer with usb peripheral or OTG and the g_dbpg driver. Single Board computers typically have that. | ||
| | |||
* grub | |||
* linux kernel in its early initialisation (I'm not sure that it can be kept afterward, because, after the early initialisation, by default it tries to initialise the USB port normally) | |||
|- | |||
! [[EHCI Debug Port| Console Over USB serial port through EHCI debug port]] | |||
(sends coreboot logs over the usb debug port) | |||
| | |||
* input (probably not in coreboot) | |||
* output | |||
| | |||
* An USB debug port supported by coreboot. | |||
* To find on which usb connector it goes. | |||
* A supported dongle: | |||
** FTDI FT232H Serial adapter | ** FTDI FT232H Serial adapter | ||
| | | | ||
* grub | * grub | ||
* linux kernel | * linux kernel | ||
|- | |- | ||
! [[Spkmodem| Console trough spkmodem]] | ! [[Spkmodem| Console trough spkmodem]] |
Latest revision as of 17:01, 24 February 2018
Coreboot has various possible consoles:
Output name | direction (from the coreboot target machine point of view) | Requirements | Compatibility with software loaded after coreboot, like OS and payloads |
---|---|---|---|
Serial console
(sends coreboot logs over the serial port) |
|
|
|
Console Over EHCI debug port
(sends coreboot logs over the usb debug port) |
|
|
|
Console Over USB serial port through EHCI debug port
(sends coreboot logs over the usb debug port) |
|
|
|
Console trough spkmodem
(sends coreboot logs over the sound card) |
|
|
For writting to it from the coreboot target computer:
For reading it from a remote computer:
|
Network console
(sends coreboot logs over the network) |
|
|
For sending the logs:
For receiving the logs:
|
Cbmem console
(Ram buffer, like dmesg) |
|
|
For writting to the buffer which is in the coreboot target computer:
For reading the buffer on the coreboot target computer, after coreboot booted:
|
POST card |
|
If none of the above works for your case, you might consider:
- Trying Flash emulators to trace the code being accessed.
- Osciloscopes for hardware related lower level debuging.
- SerialICE if you can add support for your board serial or EHCI Debug Port in SerialICE