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== General ==
== General ==


=== What is LinuxBIOS? ===
=== What is coreboot? ===


LinuxBIOS aims to replace the normal BIOS found on PCs, Alphas, and other machines with a Linux kernel that can boot Linux from a cold start. LinuxBIOS is primarily Linux - about 10 lines of patches to the current Linux kernel. Additionally, the startup code - about 500 lines of assembly and 5000 lines of C - executes 16 instructions to get into 32-bit mode and then performs DRAM and other hardware initialization required before Linux can take over.  
'''coreboot''' (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers.


Our primary motivation for the project was maintenance of large clusters, but not surprisingly interest and contributions have come from people with varying backgrounds.  
It performs just a little bit of hardware initialization and then executes what is called a [[Payloads|payload]].


=== Why do we need LinuxBIOS? ===
Some of the many possible payloads are: a [[Linux]] kernel, [[FILO]] (a GRUB-like bootloader for booting from disk), [[GRUB2]], [http://www.openbios.org/Open_Firmware Open Firmware], [[Etherboot]]/[[GPXE]], [[SeaBIOS]] (for booting Windows XP, Windows Vista, Windows 7, NetBSD and Linux), and [[Payloads|many others]].
 
The initial motivation for the project was maintenance of large clusters, but unsurprisingly, interest and contributions have come from people with varying backgrounds. The latest version of coreboot can be used in a wide variety of scenarios including clusters, embedded systems, desktop PCs, servers, and more.
 
For more information, see [[History]].
 
=== Why do we need coreboot? ===
 
==== Why do we need coreboot for cluster maintainance? ====


Current PCs used as cluster nodes depend on a vendor-supplied BIOS for booting. The BIOS in turn relies on inherently unreliable devices such as floppy disks and hard drives to boot the operating system. In addition, current BIOS software is unable to accommodate non-standard hardware making it difficult to support experimental work. The BIOS is slow and often erroneous and redundant and, most importantly, maintenance is a nightmare. Imagine walking around with a keyboard and monitor to every one of the 128 nodes in a cluster to change one BIOS setting.  
Current PCs used as cluster nodes depend on a vendor-supplied BIOS for booting. The BIOS in turn relies on inherently unreliable devices such as floppy disks and hard drives to boot the operating system. In addition, current BIOS software is unable to accommodate non-standard hardware making it difficult to support experimental work. The BIOS is slow and often erroneous and redundant and, most importantly, maintenance is a nightmare. Imagine walking around with a keyboard and monitor to every one of the 128 nodes in a cluster to change one BIOS setting.  


The LinuxBIOS gunzip's the Linux kernel straight out of NVRAM and essentially requires no moving parts other than the fan. It does a minimal amount of hardware initialization before jumping to the kernel start and lets Linux do the rest. As a result, it is much faster (current record 3 seconds), which has sparked interest in the consumer electronics community as well. Moreover, updates can be performed over the network.  
coreboot with Linux as a [[Payloads|payload]] (other payloads are possible!) gunzip's the Linux kernel straight out of NVRAM and essentially requires no moving parts other than the CPU fan. It does a minimal amount of hardware initialization before jumping to the kernel start and lets Linux do the rest. As a result, it is much faster (current record: 3 seconds), which has sparked interest in the consumer electronics community as well. Moreover, updates can be performed over the network.  
 
Using a real operating system to boot another operating system provides much greater flexibility than using a simple netboot program or the BIOS. Because Linux is the boot mechanism, it can boot over standard '''Ethernet''' or over other interconnects such as '''Myrinet''', '''Quadrics''', or '''SCI'''. It can use SSH connections to load the kernel, or it can use the '''InterMezzo caching file system''' or traditional '''NFS'''. Cluster nodes can be as simple as they need to be — perhaps as simple as a CPU and memory, no disk, no floppy, and no file system. The nodes will be much less autonomous thus making them easier to maintain.
 
==== Why do we need coreboot for other purposes? ====
 
Some aspects of '''DRM''' are not travelling well with the idea of a free computer system. As many computer magazines already pointed out, there may be future restrictions imposed by BIOSes, that a customer is little aware of before purchase and might not harmonize with the idea of freedom and/or security in some cases.
 
=== Who is working on coreboot? ===
 
The coreboot project was started in the winter of 1999 in the '''Advanced Computing Laboratory at Los Alamos National Laboratory (LANL)''' by [[User:Rminnich|Ron Minnich]]. Two undergraduate students, James Hendricks and Dale Webster spent their winter vacation putting together the proof of concept implementation.
 
Since then, a [[Contributors|long list of people have contributed]] both in discussions and actual code. Please don't be shy and let us know if you are missing from the list. It's not a purposeful omission, just an unfortunate mistake.
 
=== Who is funding coreboot? ===
 
The coreboot project was initially funded by the Los Alamos Computer Science Institute and the Department of Energy's Office of Science.
 
See also the [[Sponsors|list of coreboot sponsors]].
 
== Users ==
 
=== Will coreboot work on my machine? ===


Using a real operating system to boot another operating system provides much greater flexibility than using a simple netboot program or the BIOS. Because Linux is the boot mechanism, it can boot over standard Ethernet or over other interconnects such as Myrinet, Quadrics, or SCI. It can use SSH connections to load the kernel, or it can use the InterMezzo caching file system or traditional NFS. Cluster nodes can be as simple as they need to be - perhaps as simple as a CPU and memory, no disk, no floppy, and no file system. The nodes will be much less autonomous thus making them easier to maintain.  
See the [[Supported Motherboards]] page for which mainboards are supported, and also the list of [[Supported Chipsets and Devices]]. See the [[Products]] page for a list of vendors selling products running coreboot. Finally, you could look at the coreboot source tree, in src/mainboard.


=== Who is working on LinuxBIOS? ===
If your board is not already supported, it will likely take you years of work to port coreboot to operate correctly on it unless you have experience with firmware level C development and good knowledge of the underlying (x86 or ARM) architecture.


The LinuxBIOS project was started in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory by Ron Minnich. Two undergraduate students, James Hendricks and Dale Webster spent their winter vacation putting together the proof of concept implementation.
If you do not see your board in the above sources, please send the following to the [[Mailinglist|mailing list]]:


Since then, a long list of people have contributed both in discussions and actual code. See our contributors page for details. Please don't be shy and let us know if you are missing from the list. It's not a purposeful omission, just an unfortunate mistake.  
* Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details.
* Step 2: Linux "'''lspci -tvnn'''" output for your system, generated by booting Linux via the original BIOS and runnning lspci.
* Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "'''[[superiotool]] -dV'''").
* Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "'''[http://flashrom.org flashrom] -p internal -V'''"
* Step 5: URL to the mainboard specifications page (optional).
* Step 6: Any other relevant information you can provide.


=== Who is funding LinuxBIOS? ===
If you can't do step 1 above, please describe (as best you can) the specific CPU chip and the chipset used on the mainboard.


The LinuxBIOS project is funded by the Los Alamos Computer Science Institute and the Department of Energy's Office of Science.  
Usually in less than a day, someone will respond on the coreboot mailing list, most often with bad news. However it is possible that your mainboard is supported in the main coreboot source tree, or that support is currently in development, so it won't hurt to ask. It's also possible (and unfortunately, likely) that the manufacturer will not release information needed to provide coreboot support. In the latter case, please let the manufacturer know that you want coreboot support and his failure to release chipset information is making that very difficult.


=== Will LinuxBIOS work on my machine? ===
=== What commercial products use coreboot? ===


See the status page for which mainboards are supported. Also, see the products page for a list of vendors selling products running LinuxBIOS.  
See the [[products]] page.


=== What commercial products use LinuxBIOS? ===
=== Which different operating systems will coreboot boot? ===


See the products page.  
coreboot should support almost any modern operating system. To support operating systems that use [http://en.wikipedia.org/wiki/BIOS_interrupt_call BIOS calls], [[SeaBIOS]] is mandantory, as coreboot doesn't provide these by itself:


=== How can I help with LinuxBIOS? ===
* Linux
* Plan 9
* FreeDOS (via [[SeaBIOS]])
* Windows 2000, XP, Vista, 7(RC) (via [[SeaBIOS]], the boot loader requires BIOS)
* NetBSD, MirBSD (via [[SeaBIOS]] as at least the boot loader requires BIOS)


Contact [[User:Rminnich|Ron Minnich]] for projects related to LinuxBIOS.
coreboot does '''not''' natively support:


== Developer ==
* We have tested some of the BSD OSes and have seen, that FreeBSD for example makes BIOS calls, which is not supported by coreboot. Possibly with help of [[SeaBIOS]], it may be possible to boot FreeBSD like it is now, but the right thing to do, is to remove FreeBSD's dependence on BIOS calls.
* Windows versions older than Windows 2000, as they make BIOS calls ([[SeaBIOS]] might help)
* [http://www.menuetos.net/ MenuetOS], as it makes BIOS calls ([[SeaBIOS]] might help)
 
Please feel free to test booting any of the above using [[SeaBIOS]] and report to the coreboot mailing list.
 
=== What chipsets and Super I/O devices are supported? ===
 
See the [[Supported Chipsets and Devices]] page.


=== Where is the mailing list archived? ===
=== Where is the mailing list archived? ===


The best archive out there is at the University of Maryland. (jdarby: can someone hunt out this url? I don't know it offhand.)
See [[Mailinglist]].


In addition, we've pieced together an archive that dates back to about the beginning of 2000 (including messages that were going to the freebios and openbios mailing lists).  
=== Is there a coreboot IRC channel? ===
 
Yes, see [[IRC]].


=== Where do I get the code? ===
=== Where do I get the code? ===


See the [[Download_freebios_v2|download page]].
See the [[Download coreboot|download page]].


=== How do I build? ===
=== How do I build coreboot? ===


See the documentation. For help generating a config file, see Generate a config file. (jdarby: this needs to be wikiized)
See the [[Build HOWTO]].


=== Why is the code so complicated and what can I do to make it easier? ===
=== How can I help with coreboot? ===
 
There are many ways how you can help us:
 
* You can ask for a Wiki account. Send a private message with your preferred username and email to ''pgeorgi'' or ''stefanct'' in the #coreboot [[IRC]] channel at freenode.net.
* Promote coreboot, tell all your friends about it, blog about it etc.
* Test coreboot, report any bugs you find to our [[Mailinglist|mailinglist]] or to our [[Development_Guidelines#Bug-Tracker|bug tracker]], or let us know about any suggestions for improvements you have.
* Help us to make the list of [[Supported Motherboards]] and the list of [[Supported Chipsets and Devices]] bigger by contributing code. Please also read the [[Development Guidelines]] in that case.
* If you have a mainboard with USB2 (EHCI-controller) you can look if it supports the [[EHCI Debug Port]] and mail the information to us, if it is not already there.
** If you are familiar with microcontroller development, you might be able to build a debugging tool for the [[EHCI Debug Port]]. If you are successful, we like to hear about it.
* Test, if QNX or Solaris are able to boot on a mainboard with coreboot.
* Have a look at the list of open issues/bugs in our [[Mailinglist|mailinglist]] (as current [[Development_Guidelines#Bug-Tracker|bug tracker]] is dead) and try to reproduce them or (preferrably) fix them.
* Contact [[User:Rminnich|Ron Minnich]] or [[User:Stepan|Stefan Reinauer]] for bigger projects related to coreboot.
* Contact us on the [[Mailinglist|mailing list]] if you have any further questions or suggestions.
 
=== What do the abbreviations in this wiki stand for? ===
 
See [[Glossary]].
 
=== Can I play the latest PC games on a coreboot platform? ===
 
Of course.
 
The current performance coreboot compatible x86-64 motherboard is the [[Board:asus/kgpe-d16|KGPE-D16]] which has dual PCI-e x16 2.0 slots, 192GB max RAM and can support fast CPU's such as the G34 16 core Opteron 6386SE, 6287SE and 6284SE - with one of those the bottleneck will be always be GPU related if you are playing a highly multi-threaded game.
 
If you aren't using the computer for something very important you can save a lot of money and have an affordable libre firmware gaming platform by getting a used CPU. You can even use IOMMU-GFX to have multiple separate VM's and thus have more than one player on the same machine (needs one gfx card per VM)
 
If you do not want to have to buy an SSI-EEB compatable case there is also the [[Board:asus/kcma-d8|KCMA-D8]] which is the KGPE-D16's regular ATX little brother, although the CPU's max out at 8 cores per and there aren't as many PCI-e slots (no dual x16 so no crossfire).
 
NOTE: game needs to be highly multithreaded due to poor c32/g34 opteron single threaded performance, having half core turbo functional helps with this. Thus brand new and old games work great but games from 3-6 years ago may work poorly.
 
Opteron C32/G34 CPU's to buy for gaming:
 
G34 16 core:
6386SE
6287SE
6284SE
 
G34 8 Core:
6328 (approx FX-8310)


The reason is the complexity of the problem. We support a lot of hardware, and a given chip on a given board will most likely not be configured quite the same as the same chip on some other board.
C32 8 Core
4386


To help make code navigation easier, pick a target and build that target. Then, in the build directory, type make tags or make etags to get your favorite tags file.  
Note: On multi CPU or 16 core setups you will have poor performance and stuttering if your OS does not properly allocate NUMA memory.


=== What chipsets are supported? ===
== Developers ==


See status for the most up-to-date info.. (jdarby: this needs to be wikiized)
=== Where can I buy BIOS chips (empty or pre-flashed)? ===


=== What is this POST card thing? ===
When developing or simply trying out coreboot you always need a means to revert to your old BIOS in case something goes wrong. One way to do this is to get an extra BIOS chip (PLCC32, DIP32, DIP8, or other) and copy your original BIOS image onto that chip (using [http://flashrom.org flashrom], for example). If you have a socketed BIOS (not soldered onto the mainboard), you can hot-swap the chips while your computer is running (Do not hot swap with your hands - You must use an insulated chip removal tool to avoid a short-circuit)


A POST card will save your life. The term POST means Power On Self Test and comes from the original IBM specifications for the BIOS. Port 80 is a pre-defined port to which programs can output a byte. The POST card displays the byte in hex on its 2 digit display. We use a lot of POST codes in LinuxBIOS, so if you can tell us the POST code you see, we will have some idea of what happened.  
You have several options to get spare BIOS chips:
* Most local or online electronics dealers carry some, for example:
** Germany:
*** http://www.bios-chip.com / http://www.bios-express.de (same company)
*** http://www.bios-fix.de
*** http://www.bios-chips.com
*** http://www.conrad.de
*** http://www.endrich.com/de/site.php/47385 (it's unknown whether they ship small quantities)
*** http://www.chip-service.de
*** http://www.neumueller.com/
** UK:
*** http://bios-repair.co.uk/
** US:
*** http://avnet.com
*** http://mouser.com
*** http://semiconductorstore.com/
* You can search eBay for BIOS chips (either empty ones or pre-flashed ones).
* You can rip out chips from old/broken mainboards and re-use them (you can check flea markets, eBay, etc. for cheap and/or broken mainboards).


If your LinuxBIOS machine is working properly, you will see it count up from 0xd0 to 0xd9 (while it is gunzipping the kernel) and then display 0x98 (Linux idle loop).
=== What kind of hardware tools do I need? ===


=== How do I contribute my changes? ===
See the [[Developer Manual#Required_hardware_and_software_tools_for_developers|hardware tools section]] of the [[Developer Manual|developer's manual]].


Any one without commit privileges (which is most of you) need to get changes approved by Ron Minnich.
=== How do I use a null-modem cable to get coreboot debugging output over a serial port? ===


=== How do I re-flash the BIOS? ===
* First, you'll want to set up a terminal program, e.g. '''minicom''' correctly.
$ minicom -s
  -> Serial port setup
  -> Press A and enter your COM device (ttyS0 or ttyS1 or ttyUSB0, depending on your COM port)
  -> Press E and choose "115200 8N1" (default)
  -> Disable Hardware and Software Flow Control (via F and G)
  -> Press enter to leave the menu
  -> Save setup as..
  ->  Enter "lb"
  -> Exit from minicom
* From now on, you can start minicom with the obove settings simply by typing:
$ minicom -o lb


Download the appropriate flash update utility. Build the romimage as explained above and use the flash update utility to update the BIOS. Be warned that not all update utilities allow you to load your own BIOS image. For example, Intel decided to disallow it for the MS440GX mainboard (probably after hearing about us!) Here are some mainboard specific directions.
=== What documentation do I need? ===


SiS 630/950 M/Bs
As much documentation as you can possibly get your hands on. At minimum, you will need the docs for the chipset.
Ollie Lho provided us with flash utilities for these boards under freebios/util/sis.
flash_on turns on the flash write enable. This needs to be run before loading the DoC drivers.
There have been reports of people getting coreboot working by booting with the OEM BIOS. Then, they would read the static contents of the PCI config registers after boot. coreboot is then built to match the static contents read from the PCI config registers.  
flash_rom allows you to use your SiS 630/950 M/Bs as a flash programmer. It currently supports JEDEC flash parts, AMD am29f040b models, MXIC MX29F002 models, and SST28SF040C models.  
Intel L440GX
Get the System Update Package directly from Intel. mcopy the ten files created from running make phlash onto the Intel flash burner disk and use the update utility to burn the BIOS. To restore the original BIOS, set the recovery boot jumper on the motherboard, put the floppy in, and it will load and reflash the original BIOS.  
How do I actually burn a flash ROM?


Buy your favorite flash burner (we use a Needham Electronics EMP 30). Use make floppy to create the romimage and copy it to a floppy. Then use the provided software to burn the flash.  
The problem with this approach is that chipsets generally require dynamic vs static configuration values during their initialization. The configuration register contents will change from one stage of initialization to the next. Since the contents of the registers read is only the final state of the configuration registers, the chipset won't be properly initialized if these are the only configuration values used.


=== How do I burn a DoC? ===
Getting a mainboard up without chipset docs can be a very long and involved process.


Currently, only the DoC Millennium is supported. See the documentation.
=== What if my chipset docs are covered by an NDA? ===


=== Can I do any serious damage mucking around with this stuff? ===
If the documentation for your chipset covered by a NDA with no source release agreement, you won't be able to release your code back to the coreboot project in general, or you will violate the GPL.
Many vendors accept releasing the source code, produced after reading such specs, while they don't allow the specs themselves to be revealed. Also, you can offer them the opportunity to review your code, before releasing it to the public.


Any time you stick your hand into an open machine while the power is on, you're risking life and limb. That said, there are also some other not-so-nice things that can happen if you mess up (not that we would know).
=== Why is the code so complicated and what can I do to make it easier? ===


* Incorrect inserstion of the flash (1 casualty)
The reason is the complexity of the problem. We support a lot of hardware, and a given chip on a given board will most likely not be configured quite the same as the same chip on some other board. To help make code navigation easier, pick a target and build that target. Then, in the build directory, type make tags or make etags to get your favorite tags file.
* Incorrect jumper settings (1 casualty)
* Aggressive and/or inappropriate use of metal objects such as screwdrivers (2 casualties)
* Miscellaneous miswirings and mishandlings (3+ casualties)


=== A note on electrostatic discharge (ESD) and ESD protection (thanks to Bari Ari) ===
=== How do I contribute my changes? ===


ESD can damage disk drives, boards, DoC's and other parts. The majority of the time, ESD events cause the component to degrade, but not fail testing procedures, resulting in failure at a later date. Because components do not fail immediately, technicians often underestimate the cost of not using ESD prevention measures. Provide at minimum some ESD protection by wearing an antistatic wrist strap attached to the chassis ground on your system when handling parts.  
Please carefully read the [http://coreboot.org/Development_Guidelines Development Guidelines] for more information.


Always handle boards carefully. They can be extremely sensitive to ESD. Hold boards only by their edges. After removing a board from its protective wrapper or from the system, place it component side up on a grounded, static free surface. Use a conductive foam pad if available. Do not slide the board over any surface.
=== How do I identify the BIOS chip on my mainboard? ===


To further reduce the chances of ESD, you should create an ESD safe workstation that includes at minimum:  
Please see [http://flashrom.org/Technology].


* Conductive rubber mat, with a lead wire that can be connected to a metal surface to create a ground.
=== How do I (re-)flash the BIOS? ===


* ESD wrist strap, which has a resistor inside the strap and a lead wire that can be connected to a metal surface as a ground. The grounding wire on the wrist strap should have between 1 and 10 Megaohms of resistance. The resistor should protect you in case you come in contact with a voltage source. If the resistor is bad or not included, the wrist strap is useless. An accidental shock could be serious and even deadly!
==== Out of mainboard BIOS (re)flash ====


* Table or workspace that is clean, clear of dust, and away from electrical machinery or other equipment that generates electrical currents.  
If the BIOS chip is socketed, it can be removed and flashed in a rom/flash burner and quickly re-installed.


The idea is to ensure that all components you are going to interact with have the same charge. By connecting everything to the computer case, you ensure that the components of the case, the chair, and your body all have the same charge. If every object has the same charge, the electrons will not jump from one object to another minimizing the risk of ESD damage.  
You have the option of using the [http://www.flashrom.org/Supported_hardware external programmers supported by flashrom] or some other external programmer which comes with its own software. Depending on the flash chip type, various options exist. For older parallel flash chips, some of these burners cost $700 and more plus they complete a flash in 30 seconds (like the [http://www.conitec.net/english/galep5.php Conitec Galep V]), but if you are willing to wait 5 minutes for a flash and manually set DIP switches, the Enhanced Willem Universal Programmer will do the job for only $40-60 USD. There are several models of the Willem Programmer, each supporting many chips, but not all, so be sure to get one that supports your BIOS chip. You could also use the [http://www.flashrom.org/Paraflasher Paraflasher] which is a really low-cost programmer with parts sold for $20 or less. The [http://flashrom.org flashrom] wiki has a list of hardware you can use for programming.


=== How do I put a filesystem on DoC? ===
If your chip is PLCC, you will also need the push pin trick or a PLCC chip extractor/puller or just thread nylon string under the PLCC chip from corner to corner and yank up it straight up. Read more about chip extraction in the [[Developer_Manual/Tools#Chip_removal_tools|developer manual]].
OK, here is a little HOWTO on how to set up MTD with a file system.  


This is a m810lmr, booting out of DoC. I am going to reserve the first 2M for kernel. So the layout will be the first 2M for linuxbios and kernel, and 6M for a file system. Kernel is 2.4.17, with linux-2.4.17-sis.patch from linuxbios source tree, and config-2.4.17-sis from the linuxbios source tree. Mainboard is the pcchips m810lmr.
==== Inside mainboard BIOS (re)flash ====


So I:  
Download the appropriate flash update utility. Build the coreboot image as explained above and use the flash update utility to update the BIOS. Be warned that not all update utilities allow you to load your own BIOS image. NOTE: Many vendor specific flash utilities refuse to write "foreign" BIOS images, such as coreboot.
modprobe doc2001
modprobe docprobe
dmesg


which shows:
Therefore we suggest that you use the universal flash utility called [http://www.flashrom.org/ flashrom] which was developed and improved by many coreboot developers, and it works under Linux/*BSD/MacOSX/Solaris/DOS.


DiskOnChip Millennium found at address 0xFFFC8000
Example:
Flash chip found: Manufacturer ID: 98, Chip ID: E6 (Toshiba TC58V64AFT/DC)
  bash$ sudo ./flashrom -V
  1 flash chips found. Total DiskOnChip size: 8 MiB
  flashrom v0.9.2-r1000 on Linux 2.6.34-rc7-git5 (x86_64), built with libpci 3.1.7, GCC 4.4.3
mtd: Giving out device 0 to DiskOnChip Millennium
  flashrom is free software, get the source code at http://www.flashrom.org
Ignoring DiskOnChip Millennium at 0xFFFCA000 - already configured
  Ignoring DiskOnChip Millennium at 0xFFFCC000 - already configured
Ignoring DiskOnChip Millennium at 0xFFFCE000 - already configured
Ignoring DiskOnChip Millennium at 0xFFFD0000 - already configured
Ignoring DiskOnChip Millennium at 0xFFFD2000 - already configured
Ignoring DiskOnChip Millennium at 0xFFFD4000 - already configured
Ignoring DiskOnChip Millennium at 0xFFFD6000 - already configured
(etc..)
Now I need MTD utilities.  
  So I:  
cvs -d :pserver:anoncvs@cvs.infradead.org:/home/cvs login
CVS password:
   
   
  (password is anoncvs)
  No coreboot table found.
  Then:  
Found chipset "Intel ICH9", enabling flash write... OK.
  cvs -d :pserver:anoncvs@cvs.infradead.org:/home/cvs co mtd
  This chipset supports the following protocols: FWH,SPI.
Calibrating delay loop... 663M loops per second, 100 myus = 199 us. OK.
  Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000.
No operations were specified.


Forget the drivers and such, you don't need them. What you need is the tools.  
Alternatively you could either use the DOS [http://www.rainbow-software.org/uniflash/ uniflash] utility, or use its source code, which is also available for download from the uniflash site (in Turbo Pascal 7) as a reference for adding support for your flash chip to [http://flashrom.org flashrom].  Uniflash supports a lot of different flash chips, and chip interfaces, but so far SPI support is only present in flashrom. You can use flashrom and uniflash for PCI expansion card flashing, such as on RTL8139 Ethernet card (32pin DIL), which allows flashing of your BIOS chip on the NIC if manufacturer provides the circuitry. Please note that flashrom and uniflash support different cards and you should check which utility supports the programmer hardware you own.
cd mtd/tools
make


Go ahead and copy the executables somewhere handy, you'll need them.  
Another tool which runs in linux is [http://sourceforge.net/projects/ctflasher/ ctflasher], but it is not maintained anymore and might not work with current Linux kernels.


Now we need to make the last 6M into a "disk". We need to format it. The tool is nftl_format, so:


[root@carly util]# ./nftl_format
===== BIOS Savior RD1 =====
$Id: nftl_format.c,v 1.17 2001/08/29 14:28:48 dwmw2 Exp $
Usage: ./nftl_format [ []]
[root@carly util]# expr 2048 \* 1024
2097152
[root@carly util]# expr 6 \* 1024 \* 1024
6291456
[root@carly util]# ./nftl_format /dev/mtd0 2097152 6291456
$Id: nftl_format.c,v 1.17 2001/08/29 14:28:48 dwmw2 Exp $
Phase 1. Checking and erasing Erase Zones from 0x00200000 to 0x00800000
Phase 2.a Writing NFTL Media Header and Bad Unit Table
Phase 2.b Writing Spare NFTL Media Header and Spare Bad Unit Table
Phase 3. Writing Unit Control Information to each Erase Unit


[http://www.ioss.com.tw/web/English/RD1BIOSSavior.html BIOS Savior RD1]


we now have a formatted disk in there. We can now partition it.  
There are some posts about the BIOS Savior RD1 that suggest its integrated flash device is of low quality; it may take 10 or more flash programming attempts to get a good update to the RD1 flash device. As a result, the following steps have proven to be successful while using the RD1:


[root@carly util]# modprobe nftl
* Step 1 - While the system is powered down, remove the original BIOS device from the mainboard and insert it into the RD1's socket.


dmesg shows LOTS of errors, since this was never partitioned ...  
* Step 2 - Insert the RD1 into the mainboard's flash BIOS socket.


Also, if you don't have /dev/nftla,
* Step 3 - Boot the system with the RD1 set to boot from the original flash device from the mainboard.
 
* Step 4 - Program the original BIOS image (or other known good BIOS image) into the RD1's integrated flash device. Do this as many times as needed until the device is properly programmed and the system boots corectly from the RD1's integrated flash device. Be sure to check the settings on the RD1 so that the proper flash device is now being programmed. If the RD1 is not set correctly the working BIOS image will be erased and the system will not boot!
 
* Step 5 - Program the test BIOS image (usually coreboot images are among this group) into the original flash device from the mainboard. The original BIOS device usually programs OK on the first attempt. Be sure to check the settings again on the RD1 so that the proper flash device is being programmed!
 
 
The RD1 has been used in the above fashion with great success on the Tyan S2885 mainboard. Unfortunately the RD1 does not work on the nVidia CK8-04 CRB mainboard. The CK8-04 CRB may require a flash device that the RD1 does not support.
 
The RD1 has worked well as a "do nothing" adapter that allows swapping the BIOS flash device between a flash burner and a mainboard without any wear to the mainboard's BIOS socket.
 
=== Can I do any serious damage mucking around with this stuff? ===


[root@carly util]# mknod /dev/nftla b 93 0
Any time you stick your hand into an open machine while the power is on, you're risking life and limb. That said, there are also some other not-so-nice things that can happen if you mess up (not that we would know).


* Incorrect insertion of the flash (1 casualty)
* Incorrect jumper settings (1 casualty)
* Aggressive and/or inappropriate use of metal objects such as screwdrivers (2 casualties)
* Miscellaneous miswirings and mishandlings (3+ casualties)


Don't use the script just yet, it makes /dev/nftla as b 93 16, which is the wrong unit #.  
remember: make sure your important data is on a disconnected drive while you experiment.


now fdisk /dev/nftla
=== A note on electrostatic discharge (ESD) and ESD protection (thanks to Bari Ari) ===


[root@carly util]# fdisk /dev/nftlA
ESD can damage disk drives, boards, DoC's and other parts. The majority of the time, ESD events cause the component to degrade, but not fail testing procedures, resulting in failure at a later date. Because components do not fail immediately, technicians often underestimate the cost of not using ESD prevention measures. Provide at minimum some ESD protection by wearing an antistatic wrist strap attached to the chassis ground on your system when handling parts.  
Command (m for help): n
Command action
e extended
p primary partition (1-4)
p
Partition number (1-4): 1
First cylinder (1-1, default 1):
Using default value 1
Command (m for help): p
Disk /dev/nftlA: 1 heads, 12224 sectors, 1 cylinders
Units = cylinders of 12224 * 512 bytes
Device Boot Start End Blocks Id System
/dev/nftlA1 1 1 6111+ 83 Linux
Partition 1 has different physical/logical endings:
phys=(768, 0, 0) logical=(0, 0, 12224)
Partition 1 does not end on cylinder boundary:
phys=(768, 0, 0) should be (768, 0, 12224)
Command (m for help): w
The partition table has been altered!
Calling ioctl() to re-read partition table.  
WARNING: If you have created or modified any DOS 6.x partitions, please see the fdisk manual page for additional information.  
Syncing disks.
[root@carly util]# mknod /dev/nftlA1 b 93 1
[root@carly util]# mke2fs /dev/nftlA1
mke2fs 1.23, 15-Aug-2001 for EXT2 FS 0.5b, 95/08/09
Filesystem label=
OS type: Linux
Block size=1024 (log=0)
Fragment size=1024 (log=0)
1528 inodes, 6111 blocks
305 blocks (4.99%) reserved for the super user
First data block=1
1 block group
8192 blocks per group, 8192 fragments per group
1528 inodes per group
Writing inode tables: done
Writing superblocks and filesystem accounting information: done


This filesystem will be automatically checked every 37 mounts or 180 days, whichever comes first. Use tune2fs -c or -i to override.  
Always handle boards carefully. They can be extremely sensitive to ESD. Hold boards only by their edges. After removing a board from its protective wrapper or from the system, place it component side up on a grounded, static free surface. Use a conductive foam pad if available. Do not slide the board over any surface.  


[root@carly util]# mount /dev/nftlA1 /mnt
To further reduce the chances of ESD, you should create an ESD safe workstation that includes at minimum:
[root@carly util]# cd /mnt
[root@carly mnt]# df .
Filesystem 1k-blocks Used Available Use% Mounted on
/dev/nftlA1 5915 13 5597 1% /mnt
[root@carly mnt]#


and so you now have an ext2 file system on the DoC.  
* Conductive rubber mat, with a lead wire that can be connected to a metal surface to create a ground.  


(Above is from [[User:Rminnich|Ron Minnich]])
* ESD wrist strap, which has a resistor inside the strap and a lead wire that can be connected to a metal surface as a ground. The grounding wire on the wrist strap should have between 1 and 10 Megaohms of resistance. The resistor should protect you in case you come in contact with a voltage source. If the resistor is bad or not included, the wrist strap is useless. An accidental shock could be serious and even deadly!


=== How do I turn off embedded sis630 devices? ===
* Table or workspace that is clean, clear of dust, and away from electrical machinery or other equipment that generates electrical currents.


From aip@cwlinux.com Mon Mar 25 08:54:07 2002
The idea is to ensure that all components you are going to interact with have the same charge. By connecting everything to the computer case, you ensure that the components of the case, the chair, and your body all have the same charge. If every object has the same charge, the electrons will not jump from one object to another minimizing the risk of ESD damage.
Date: Mon, 25 Mar 2002 22:07:54 +0800
From: Andrew Ip
To: Kei Furuuchi
Cc: linuxbios@lanl.gov
Subject: Re: How to turn off unused pci device.
Hi,
> I have pcchips m758lmr which has audio chip besides sis630.
> those functions in sis630 are not used in the motherboard.  
> But, the functions keep coming up. How do I turn off those?
The following is from Nikolai Valdych previous message. Hope this help.
-Andrew
--
Andrew Ip
Email: aip@cwlinux.com
Actualy, it was pretty simple 0x7c00 - All devices enabled, You play with first 4 bits only. Cos there are 4 devices, so you have any combination of 4 bits.
Set bit to 1 to turn off the device, bit 0 to enable it.
This is the device list:
Multimedia Audio controler
Modem controler
Ethernet sis930 controler
USB controler.
For example, to turn off Ethernet + USB it would be:
0x7c0c -> 1100 in binary (first 4 bits)
To turn off Multimedia audio :
0x7c01 -> 0001
in binary and so on... maybe there are more detail, but this is enogh for me, Ollie, again thanks!
nikolai
p.s. though my modem is not yet working..... damn driver......  


=== What is a PIRQ table? ===
=== What is a PIRQ table? ===


From Adam Sulmicki:
There's a good description of the BIOS implementation of the PIRQ in the ''red PCI book'', and here's a [http://www.microsoft.com/whdc/archive/pciirq.mspx description of the $PIR data structure].
 
I found beautfiul descrition of the BIOS implementation of the PIRQ in the red PCI book.
coreboot saves the $PIR data structure between 0xf0000 & 0x100000. Search for $PIR and then save it before copying over the BIOS.
 
I found the description of the $PIR data structure in the
See also the [http://code.coreboot.org/p/coreboot-v1/source/tree/900/trunk/util/ADLO/README ADLO README] for more information.
        http://www.microsoft.com/hwdev/archive/BUSBIOS/pciirq.asp
looking over linuxbios sources I see that it saves the $PIR data structure
somewhere between 0xf0000 & 0x100000.
so it seems I'll have to search for $PIR and then save it before copying
over our bios. sigh. hoped for some fixed address in mem.
--
Adam
http://www.eax.com      The Supreme Headquarters of the 32 bit registers


=== How do I set up etherboot with LinuxBIOS? ===
=== How do I set up etherboot with coreboot? ===


Note from Ron: I have edited this somewhat to remove Geode-specific items.  
Note from Ron: I have edited this somewhat to remove Geode-specific items.  
Line 298: Line 316:
  Cc: linuxbios@lanl.gov
  Cc: linuxbios@lanl.gov
  Subject: Re: LinuxBIOS + Etherboot HOWTO?
  Subject: Re: LinuxBIOS + Etherboot HOWTO?
   
   
  I had some trouble using LinuxBIOS + etherboot...  
  I had some trouble using LinuxBIOS + etherboot...  
   
   
  My bad, I messed up and used mkelfImage-1.6 that I got from ftp.lnxi.com, when I realized that I ought to use the one from freebios/util everything started working.  
  My bad, I messed up and used mkelfImage-1.6 that I got from ftp.lnxi.com, when I realized that I ought to use the one from freebios/util everything started working.  
   
   
  Here's what I did to get LinuxBIOS + Etherboot loading and booting a Linux kernel using TFTP.  
  Here's what I did to get LinuxBIOS + Etherboot loading and booting a Linux kernel using TFTP.  
   
   
   /Christer  
   /Christer  
   
   
  Get etherboot-5.0 from the CVS tree on etherboot.sourceforge.net.  
  Get etherboot-5.0 from the CVS tree on etherboot.sourceforge.net.  
   
   
  Modify etherboot-5.0/src/Config, comment out:  
  Modify etherboot-5.0/src/Config, comment out:  
Line 319: Line 331:
     # BIOS select don't change unless you know what you are doing
     # BIOS select don't change unless you know what you are doing
     #CFLAGS32+=    -DPCBIOS
     #CFLAGS32+=    -DPCBIOS
   
   
  and uncomment the following:  
  and uncomment the following:  
Line 327: Line 337:
     CFLAGS32+= -DLINUXBIOS -DCONFIG_TSC_CURRTICKS  -DCONSOLE_SERIAL \
     CFLAGS32+= -DLINUXBIOS -DCONFIG_TSC_CURRTICKS  -DCONSOLE_SERIAL \
               -DCOMCONSOLE=0x3f8 -DCOMPRESERVE -DCONFIG_PCI_DIRECT -DELF_IMAGE  
               -DCOMCONSOLE=0x3f8 -DCOMPRESERVE -DCONFIG_PCI_DIRECT -DELF_IMAGE  
   
   
  Compile Etherboot to make an elf file for your ethernet card:  
  Compile Etherboot to make an elf file for your ethernet card:  
   
   
     make bin32/natsemi.elf
     make bin32/natsemi.elf
   
   
  Compile and install mkelfImage from freebios/util/mkelfImage.  
  Compile and install mkelfImage from freebios/util/mkelfImage.  
   
   
  Create a bootimage to put on your TFTP server:  
  Create a bootimage to put on your TFTP server:  
Line 343: Line 348:
     mkelfImage --command-line="root=/dev/hda2 console=ttyS0,38400" \
     mkelfImage --command-line="root=/dev/hda2 console=ttyS0,38400" \
               --kernel vmlinux -o /tftpboot/kernel
               --kernel vmlinux -o /tftpboot/kernel
   
   
  Finally, make sure that your BOOT/DCHP server is answering and that the TFTP server is active.  
  Finally, make sure that your BOOT/DCHP server is answering and that the TFTP server is active.  
   
   
  Tell LinuxBIOS to boot an elf Image, and tell LinuxBIOS where it is:  
  Tell LinuxBIOS to boot an elf Image, and tell LinuxBIOS where it is:  
   
   
     option USE_ELF_BOOT=1
     option USE_ELF_BOOT=1
   
   
  I have placed natsemi.elf in the first 64k of my BIOS flash chip, and LinuxBIOS in the second 64k.  
  I have placed natsemi.elf in the first 64k of my BIOS flash chip, and LinuxBIOS in the second 64k.  
Line 361: Line 361:
     dd if=linuxbios.rom of=/dev/bios bs=64k seek=1
     dd if=linuxbios.rom of=/dev/bios bs=64k seek=1
   
   
  Finally boot LinuxBIOS.
 
  Finally boot LinuxBIOS.  
=== How do I set GEODE graphics and video? ===
 
=== How do I set GEODE video? ===
There is no Geode graphics support in coreboot. Install the Geode framebuffer driver for console graphics and the X driver for X support on your Geode Linux image. Current kernel and X distributions contain the required drivers. Until the driver loads there is only serial console output.
 
Driver source:


From christer@weinigel.se Wed Nov 27 07:47:17 2002
[http://git.kernel.org/?p=linux/kernel/git/stable/linux-2.6.23.y.git;a=tree;f=drivers/video/geode;hb=3968cb49ab01588cbf6896951780a1e411a0ec38 2.6.23 kernel framebuffer driver]
Date: 27 Nov 2002 10:55:01 +0100
From: Christer Weinigel
To: Adam Bezanson
Cc: linuxbios@clustermatic.org
Subject: Re: Geode Kernel Config
"Adam Bezanson"  writes:
> I've got an Eval card from National Semi that contains
> the SC1200. I'd like to try LinuxBios on it.
> I've downloaded both the 2.4.18 and 2.4.19 kernels to start with.
> What patches do I need to apply to the kernel?
> Is there a config file I can use to configure the kernel, or
> should I do it manually?
A normal 2.4 Linux kernel will work fine as long as you compile for a
586 CPU (CONFIG_M586), not Pentium or higher (CONFIG_M586TSC and up)
since the TSC behaves a bit differently.
If you want support for the watchdog or the GPIO pins in a 2.4 kernel,
you can find an old patch from me at:
    http://groups.google.com/groups?selm=20020226015215.20118F5B%40acolyte.hack.org&oe=UTF-8&output=gplain
An updated version of this patch has been included in Linux 2.5. Alan
Cox' 2.5 kernel also has support for doing DMA on the SC1200 IDE
controller; I don't know if there is a corresponding patch for 2.4.
Other than that, take a look at the freebios/src/mainboard/nano/nano
directory and make a copy of it. All you should have to do is to
modify the Pin Multiplexing Register (PMR) and Miscellaneous Config
Register (MCR) in the Config file and to modify the irq assignments.
Depending on what you want to do, there are a few limitations with
the current LinuxBIOS on the SC1200:
    There is no video support in LinuxBIOS itself, so you won't get
    any video until you have loaded the NatSemi Geode Linux
    framebuffer driver (can be found at www.linux4.tv under the
    heading SP1SC10 Platform Image).
    There is no SMM/VSA support at all, this means that anything
    relying on it won't work.  What this means is that Audio won't
    work.
Other than that everything works fine, IDE in PIO mode, the PCI bus,
watchdog, GPIOs, everything.
  /Christer
--
"Just how much can I get away with and still go to heaven?"
Freelance consultant specializing in device driver programming for Linux
Christer Weinigel  http://www.weinigel.se
_______________________________________________
Linuxbios mailing list
Linuxbios@clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios


[http://gitweb.freedesktop.org/?p=xorg/driver/xf86-video-amd.git;a=summary X.org driver]


=== How do I set up testbios? ===
=== How do I set up testbios? ===


From daubin@actuality-systems.com Wed Oct  6 10:23:10 2004
Please read the [http://coreboot.org/FAQ/Obsolete#How_do_I_set_up_testbios.3F testbios FAQ].
Date: Tue, 5 Oct 2004 15:19:24 -0400
 
From: Dave Aubin
=== /usr/sbin/iasl: Command not found ===
To: linuxbios@clustermatic.org
 
  Subject: RE: Testbios help with nvidia 6800Gt and simple how to
If you see this error, you have to install ''iasl'', Intel's ASL Optimizing Compiler:
   
 
I've taken the time to put together a simple testbios faq.
* '''SUSE''' ships it in the '''pmtools''' package ([ftp://ftp.gwdg.de/pub/opensuse/distribution/SL-10.0-OSS/inst-source/suse/x86_64/pmtools-20050823-3.x86_64.rpm pmtools-20050823-3.x86_64.rpm], [ftp://ftp.gwdg.de/pub/opensuse/distribution/SL-10.0-OSS/inst-source/suse/i586/pmtools-20050823-3.i586.rpm pmtools-20050823-3.i586.rpm]). If you want to run rpmbuild --rebuild: [ftp://ftp.gwdg.de/pub/opensuse/distribution/SL-10.0-OSS/inst-source/suse/src/pmtools-20050823-3.src.rpm pmtools-20050823-3.src.rpm].
I hope it is helpful. Feedback and additions are welcome.  
* '''Debian''' ships it in the '''iasl''' package (''apt-get install iasl'').
* You can also download the [http://acpica.org/downloads/unix_source_code.php latest version of the source code].
  Thanks,
 
  Dave
=== How can I write to POSTcard port 0x80 from userspace? ===
[https://mail.coreboot.org/pipermail/coreboot/2006-November/017091.html This] might be useful in some situations, and to output a number to a POST card:
==== Testbios (vgabios) Faq ====
 
  printf "\001" | dd bs=1 seek=128 of=/dev/port
 
or using [https://github.com/adurbin/iotools iotools]:
  iotools io_write8 0x80 0x42
 
In case of linux commands above do output to POST card, but the value is immediately replaced by 0x00 due to [https://github.com/torvalds/linux/blob/v4.2/arch/x86/boot/boot.h#L78 io_delay]. Further explanations can be found on [https://lists.gt.net/linux/kernel/260809 kernel mailinglist archive]
 
 
In DOS (not Windows XP) use:
  mov al, 42; out al, 80h
To output 42 type
  o 80 42
in DOS [http://help.fdos.org/en/hhstndrd/base/debug.htm debug.exe].
 
When using LPT (parallel port) POST card - write to port assigned to parallel port, eg. 0x3BC, 0x378, 0x278. Some SuperIOs/EmbeddedControllers will decode 0x80 like ENE KB926
 
=== Is coreboot applying x86 microcode patches? ===
 
And if yes, can they be modified?
 
Answer: Yes, coreboot is applying microcode patches on AMD and Intel CPUs. However, this field is little documented, so coreboot uses only unmodified, vendor-provided microcode. Few people think, that system design can seriously be improved by modifications here ( �Code patches mostly disable erraneous functions and opcodes).
 
=== How can I retrieve a good video BIOS? ===
 
Note: If you are following these instructions to build coreboot for your motherboard, this is only necessary if you have a motherboard with an embedded VGA card. If your VGA is a PCI / PCI-Express add-on card, coreboot will find and run the ROM by itself.
 
See [[VGA_support]] for the details.


Date: 10/5/2004
<!--- Anton Borisov has released a number of tools under the GPL (v2) to extract the VGA BIOS from the BIOS ROM images provided by the supplier of your motherboard.
Author(s): David Aubin  daubin@actuality-systems.com


Purpose: Testbios is an i386 emulator that sits on top of userspace linux.  It's primary purpose is to provide program video rom's in to the cached memory area.
You can download them here:


===== Where to obtain testbios =====
* Award BIOS:
** http://kaos.ru/biosgfx/download/awardeco-0.2.src.tar.gz
** http://ftp.debian.org/debian/pool/main/a/awardeco/awardeco_0.2.orig.tar.gz
* AMI BIOS:
** http://www.kaos.ru/biosgfx/download/AmiDeco_0.31e.src.tar.gz
** http://ftp.debian.org/debian/pool/main/a/amideco/amideco_0.31e.orig.tar.gz
* Phoenix BIOS:
** http://www.kaos.ru/biosgfx/download/PhoenixDeco_0.33.src.tar.gz
** http://ftp.debian.org/debian/pool/main/p/phnxdeco/phnxdeco_0.33.orig.tar.gz
* Insyde BIOS:
** http://www.kaos.ru/biosgfx/download/InsyDeco_0.3.src.tar.gz
** (no alternative download location available, sorry)


Testbios(vgabios) can be retrieved from the linuxbios/freebios source tree: [http://www.linuxbios.org/developer/download/index.html]
See the [[Tyan S2881|Tyan S2881 Build Tutorial]] for more information on how to use these tools.
--->


===== Prerequisites =====
== Errors ==


You must have installed pci-utils
=== ERROR: Not enough MTRRs available! ===
* Get http://atrey.karlin.mff.cuni.cz/~mj/pciutils.shtml
There are 8 dynamic MTRRs available on x86.


===== How to build testbios =====
This message tells you that there's an error with PCI device resources.
* cd freebios/util/vgabios
* Edit ./Makefile and fill in the correct values for your environment (I build on a 64 AMD so my makefile looks like this)


Begin ./Makefile for x64:
It might be an error in the PCI handling code or the devicetree.
CC      =  gcc
ARCH    := $(shell uname -m | sed -e s,i[3456789]86,i386,)
INCLUDE  =  -I ../pciutils-2.1.11
CFLAGS  =  -Wall -Ix86emu/include -O2 -g $(INCLUDE)
INTOBJS  =  int10.o int15.o int16.o int1a.o inte6.o
OBJECTS  =  testbios.o helper_exec.o helper_mem.o $(INTOBJS)
LDFLAGS  =  -static-libgcc -static
LIBS    =  x86emu/src/x86emu/libx86emu.a ../pciutils-2.1.11/lib/libpci.a
# user space pci is the only option right now.
OBJECTS += pci-userspace.o
ifeq ($(shell if test "$(ARCH)" == "x86_64" ; then echo 1; fi), 1)
        CFLAGS +=-m32 -march=i386
        endif
        all: testbios
        testbios: $(OBJECTS) $(LIBS)
                $(CC) $(CFLAGS) -o testbios $(OBJECTS) $(LDFLAGS)
$(LIBS)
helper_exec.o: helper_exec.c test.h
x86emu/src/x86emu/libx86emu.a:
        $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux
        clean:
                $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux clean
                rm -f *.o *~ testbios
        distclean: clean
                $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux clean
End ./Makefile


* Edit ~vgabios/x86emu/src/x86emu/makefile.linux and fill in the correct values for your environment (I build on a 64 AMD so my makefile looks like this)
== Can I put coreboot into a PCI expansion ROM? ==


Begin ~vgabios/x86emu/src/x86emu/makefile.linux:
Short answer: NO.
#############################################################################
#
#                                              Realmode X86 Emulator Library
#
#              Copyright (C) 1996-1999 SciTech Software, Inc.
#
#
<nowiki>========================================================================</nowiki>
#
#  Permission to use, copy, modify, distribute, and sell this software and
#  its documentation for any purpose is hereby granted without fee,
#  provided that the above copyright notice appear in all copies and that
#  both that copyright notice and this permission notice appear in
#  supporting documentation, and that the name of the authors not be used
#  in advertising or publicity pertaining to distribution of the software
#  without specific, written prior permission.  The authors makes no
#  representations about the suitability of this software for any purpose.
#  It is provided "as is" without express or implied warranty.
#
#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
#  PERFORMANCE OF THIS SOFTWARE.
#
#
<nowiki>========================================================================</nowiki>
#
# Descripton:  Linux specific makefile for the x86emu library.
#
#############################################################################
TARGETLIB = libx86emu.a
OBJS=\
debug.o \
decode.o \
fpu.o \
ops.o \
ops2.o \
prim_ops.o \
sys.o
$(TARGETLIB): $(OBJS)
        ar rv $(TARGETLIB) $(OBJS)
        INCS  = -I. -Ix86emu -I../../include
        CFLAGS += -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -DDEBUG
        ARCH  := $(shell uname -m | sed -e s,i[3456789]86,i386,)
        ifeq ($(shell if test "$(ARCH)" == "x86_64" ; then echo 1; fi), 1)
                CFLAGS +=-m32 -march=i386
                endif
.c.o:
#      gcc -m32 -march=i386 -g -O -Wall -c $(CFLAGS) $(INCS) $*.c
        gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c
.cpp.o:
#      gcc -m32 -march=i386 -c $(CFLAGS) $(INCS) $*.cpp
        gcc -c $(CFLAGS) $(INCS) $*.cpp
clean:
        rm -f *.a *.o
validate:      validate.o libx86emu.a
        gcc -o validate validate.o -lx86emu -L.
End ~vgabios/x86emu/src/x86emu/makefile.linux


* Once built you could have a 32bit testbios executable made. Depending on your embedded environment you might want to have it built shared as the above example makes it static.  Just remove -static-libgcc -static from the LDFLAGS on ./Makefile if you wish to have it built shared.
Long answer:


===== How to retrieve a good video bios =====
There's little use in doing that, as a lots of initialization has already been done by the proprietary BIOS (or coreboot) by the time the PCI expansion ROM is executed. It won't be possible to run coreboot from a PCI expansion ROM after a proprietary BIOS has already been running for instance.
There are sites that have video bios roms on their website. (I know of this one for nvidia cards: [http://whitebunny.demon.nl/hardware/chipset_nvidia.html])


However you should be able to retrieve your own video bios as well with linux.
Note: The Intel ICH7 southbridge seems to allows booting from PCI ROMs ('''not''' arbitrary PCI expansion ROMs as used on graphics cards, SCSI controllers, etc.) -- maybe this should be investigated in order to check if or how it might be useful.
* Boot up a machine with a commercial bios (not linux bios) with the video card you wish to work under linux bios.
** From the command line enter:
                dd if=/dev/mem of=vgabios.bin skip=1536 count=128 or  
                dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=786432
                This assumes you card's bios is cached in 0xc0000.  You
                can see where and how much your card's bios is using by
                doing a cat iomem | grep "Video ROM"
*** dd Explained (man dd to learn more):
****  if is the location to retrieve from.
****  of is the output file (your rom image)
****  skip jumps n blocks where the default n is 512 bytes
****  count is how many blocks you wish to read
****  bs is the block size
** You now have a video bios image


===== How to use testbios =====
== Obsolete FAQ items ==
* Currently testbios only works from user space linux (10/4/04)
* Example from a linux command line or script enter the following to get your video bios programmed:
            ./testbios -s 65536 --abseg /dev/mem ./vgabios.bin
** Testbios explained
***  -s  how much of the video bios is there
***  --abseg where would you like to write this (/dev/mem default)
***  filename of video bios
***  -d diag mode
****  How to get pci busdevfn
****  lspci
****  look for your video card
***** Example:
                                        2:00:00
                                        2 (00 << 3) | 00 = 0x200
***** Example:
                                        00:12.0:
                                        0 (12 << 3) | 0 = 0x90
*** -t dump
*** -c codesegment Where do you want to start, default is 0xc0000
*** -b base  Where do you want base to be default is 0xc000
*** -i instruction pointer usually left off as the default


==== Followup to Testbios FAQ ====
Please see [[FAQ/Obsolete]] for (probably) obsolete FAQ items.
-----Original Message-----
From: linuxbios-admin@clustermatic.org
[mailto:linuxbios-admin@clustermatic.org] On Behalf Of Dave Aubin
Sent: Tuesday, October 05, 2004 2:22 PM
To: Richard Smith
Cc: linuxbios@clustermatic.org
Subject: RE: Testbios help with nvidia 6800Gt and simple how to
Hi,
Thank you:)  Yes, it was at 0xc0000-0xc7fff, which is only 32k.
But the image I got from the windows tool was 64k (double 8000).
Weird.  I would like to stay away from window tools.
The info you provided is nice.  I wish there was a way for us To make
a faq and we could add this to the testbios faq.  There Is a lot of good
info on the clustermatic list, but it is all Dispersed. 
Ron if I write a simple faq can you provide some mechanism to Allow
updates to it?
Thanks,
Dave
-----Original Message-----
From: Richard Smith [mailto:rsmith@bitworks.com]
Sent: Tuesday, October 05, 2004 2:16 PM
To: Dave Aubin
Cc: linuxbios@clustermatic.org
Subject: Re: Testbios help with nvidia 6800Gt and simple how to
Dave Aubin wrote:
> It seems my dd returned an unusable binary.  I found a good binary for
> The nvidia card from here:
> http://whitebunny.demon.nl/hardware/chipset_nvidia.html
>
I was wondering about your dd command that but I had not had a chance to
respond yet.
This is what I use:
dd if=/dev/mem of=vbios.bin bs=1k count=64 skip=786432
That will rip the bios from 0x0c0000.  You can verify that you actually
have bios there with
  'hd -s 0x0c0000 -n 256 /dev/mem'
in some cases it may be located at 0x0e0000 rather than 0x0c0000.
It should start with the 0x55aa (Little endian) or 0xaa55 (big endian)
and futher on you should see some text identifying the bios.
--
Richard A. Smith
_______________________________________________
Linuxbios mailing list
Linuxbios@clustermatic.org
http://www.clustermatic.org/mailman/listinfo/linuxbios

Latest revision as of 18:41, 5 March 2018

General

What is coreboot?

coreboot (formerly known as LinuxBIOS) is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers.

It performs just a little bit of hardware initialization and then executes what is called a payload.

Some of the many possible payloads are: a Linux kernel, FILO (a GRUB-like bootloader for booting from disk), GRUB2, Open Firmware, Etherboot/GPXE, SeaBIOS (for booting Windows XP, Windows Vista, Windows 7, NetBSD and Linux), and many others.

The initial motivation for the project was maintenance of large clusters, but unsurprisingly, interest and contributions have come from people with varying backgrounds. The latest version of coreboot can be used in a wide variety of scenarios including clusters, embedded systems, desktop PCs, servers, and more.

For more information, see History.

Why do we need coreboot?

Why do we need coreboot for cluster maintainance?

Current PCs used as cluster nodes depend on a vendor-supplied BIOS for booting. The BIOS in turn relies on inherently unreliable devices such as floppy disks and hard drives to boot the operating system. In addition, current BIOS software is unable to accommodate non-standard hardware making it difficult to support experimental work. The BIOS is slow and often erroneous and redundant and, most importantly, maintenance is a nightmare. Imagine walking around with a keyboard and monitor to every one of the 128 nodes in a cluster to change one BIOS setting.

coreboot with Linux as a payload (other payloads are possible!) gunzip's the Linux kernel straight out of NVRAM and essentially requires no moving parts other than the CPU fan. It does a minimal amount of hardware initialization before jumping to the kernel start and lets Linux do the rest. As a result, it is much faster (current record: 3 seconds), which has sparked interest in the consumer electronics community as well. Moreover, updates can be performed over the network.

Using a real operating system to boot another operating system provides much greater flexibility than using a simple netboot program or the BIOS. Because Linux is the boot mechanism, it can boot over standard Ethernet or over other interconnects such as Myrinet, Quadrics, or SCI. It can use SSH connections to load the kernel, or it can use the InterMezzo caching file system or traditional NFS. Cluster nodes can be as simple as they need to be — perhaps as simple as a CPU and memory, no disk, no floppy, and no file system. The nodes will be much less autonomous thus making them easier to maintain.

Why do we need coreboot for other purposes?

Some aspects of DRM are not travelling well with the idea of a free computer system. As many computer magazines already pointed out, there may be future restrictions imposed by BIOSes, that a customer is little aware of before purchase and might not harmonize with the idea of freedom and/or security in some cases.

Who is working on coreboot?

The coreboot project was started in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory (LANL) by Ron Minnich. Two undergraduate students, James Hendricks and Dale Webster spent their winter vacation putting together the proof of concept implementation.

Since then, a long list of people have contributed both in discussions and actual code. Please don't be shy and let us know if you are missing from the list. It's not a purposeful omission, just an unfortunate mistake.

Who is funding coreboot?

The coreboot project was initially funded by the Los Alamos Computer Science Institute and the Department of Energy's Office of Science.

See also the list of coreboot sponsors.

Users

Will coreboot work on my machine?

See the Supported Motherboards page for which mainboards are supported, and also the list of Supported Chipsets and Devices. See the Products page for a list of vendors selling products running coreboot. Finally, you could look at the coreboot source tree, in src/mainboard.

If your board is not already supported, it will likely take you years of work to port coreboot to operate correctly on it unless you have experience with firmware level C development and good knowledge of the underlying (x86 or ARM) architecture.

If you do not see your board in the above sources, please send the following to the mailing list:

  • Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details.
  • Step 2: Linux "lspci -tvnn" output for your system, generated by booting Linux via the original BIOS and runnning lspci.
  • Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "superiotool -dV").
  • Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "flashrom -p internal -V"
  • Step 5: URL to the mainboard specifications page (optional).
  • Step 6: Any other relevant information you can provide.

If you can't do step 1 above, please describe (as best you can) the specific CPU chip and the chipset used on the mainboard.

Usually in less than a day, someone will respond on the coreboot mailing list, most often with bad news. However it is possible that your mainboard is supported in the main coreboot source tree, or that support is currently in development, so it won't hurt to ask. It's also possible (and unfortunately, likely) that the manufacturer will not release information needed to provide coreboot support. In the latter case, please let the manufacturer know that you want coreboot support and his failure to release chipset information is making that very difficult.

What commercial products use coreboot?

See the products page.

Which different operating systems will coreboot boot?

coreboot should support almost any modern operating system. To support operating systems that use BIOS calls, SeaBIOS is mandantory, as coreboot doesn't provide these by itself:

  • Linux
  • Plan 9
  • FreeDOS (via SeaBIOS)
  • Windows 2000, XP, Vista, 7(RC) (via SeaBIOS, the boot loader requires BIOS)
  • NetBSD, MirBSD (via SeaBIOS as at least the boot loader requires BIOS)

coreboot does not natively support:

  • We have tested some of the BSD OSes and have seen, that FreeBSD for example makes BIOS calls, which is not supported by coreboot. Possibly with help of SeaBIOS, it may be possible to boot FreeBSD like it is now, but the right thing to do, is to remove FreeBSD's dependence on BIOS calls.
  • Windows versions older than Windows 2000, as they make BIOS calls (SeaBIOS might help)
  • MenuetOS, as it makes BIOS calls (SeaBIOS might help)

Please feel free to test booting any of the above using SeaBIOS and report to the coreboot mailing list.

What chipsets and Super I/O devices are supported?

See the Supported Chipsets and Devices page.

Where is the mailing list archived?

See Mailinglist.

Is there a coreboot IRC channel?

Yes, see IRC.

Where do I get the code?

See the download page.

How do I build coreboot?

See the Build HOWTO.

How can I help with coreboot?

There are many ways how you can help us:

  • You can ask for a Wiki account. Send a private message with your preferred username and email to pgeorgi or stefanct in the #coreboot IRC channel at freenode.net.
  • Promote coreboot, tell all your friends about it, blog about it etc.
  • Test coreboot, report any bugs you find to our mailinglist or to our bug tracker, or let us know about any suggestions for improvements you have.
  • Help us to make the list of Supported Motherboards and the list of Supported Chipsets and Devices bigger by contributing code. Please also read the Development Guidelines in that case.
  • If you have a mainboard with USB2 (EHCI-controller) you can look if it supports the EHCI Debug Port and mail the information to us, if it is not already there.
    • If you are familiar with microcontroller development, you might be able to build a debugging tool for the EHCI Debug Port. If you are successful, we like to hear about it.
  • Test, if QNX or Solaris are able to boot on a mainboard with coreboot.
  • Have a look at the list of open issues/bugs in our mailinglist (as current bug tracker is dead) and try to reproduce them or (preferrably) fix them.
  • Contact Ron Minnich or Stefan Reinauer for bigger projects related to coreboot.
  • Contact us on the mailing list if you have any further questions or suggestions.

What do the abbreviations in this wiki stand for?

See Glossary.

Can I play the latest PC games on a coreboot platform?

Of course.

The current performance coreboot compatible x86-64 motherboard is the KGPE-D16 which has dual PCI-e x16 2.0 slots, 192GB max RAM and can support fast CPU's such as the G34 16 core Opteron 6386SE, 6287SE and 6284SE - with one of those the bottleneck will be always be GPU related if you are playing a highly multi-threaded game.

If you aren't using the computer for something very important you can save a lot of money and have an affordable libre firmware gaming platform by getting a used CPU. You can even use IOMMU-GFX to have multiple separate VM's and thus have more than one player on the same machine (needs one gfx card per VM)

If you do not want to have to buy an SSI-EEB compatable case there is also the KCMA-D8 which is the KGPE-D16's regular ATX little brother, although the CPU's max out at 8 cores per and there aren't as many PCI-e slots (no dual x16 so no crossfire).

NOTE: game needs to be highly multithreaded due to poor c32/g34 opteron single threaded performance, having half core turbo functional helps with this. Thus brand new and old games work great but games from 3-6 years ago may work poorly.

Opteron C32/G34 CPU's to buy for gaming:

G34 16 core: 6386SE 6287SE 6284SE

G34 8 Core: 6328 (approx FX-8310)

C32 8 Core 4386

Note: On multi CPU or 16 core setups you will have poor performance and stuttering if your OS does not properly allocate NUMA memory.

Developers

Where can I buy BIOS chips (empty or pre-flashed)?

When developing or simply trying out coreboot you always need a means to revert to your old BIOS in case something goes wrong. One way to do this is to get an extra BIOS chip (PLCC32, DIP32, DIP8, or other) and copy your original BIOS image onto that chip (using flashrom, for example). If you have a socketed BIOS (not soldered onto the mainboard), you can hot-swap the chips while your computer is running (Do not hot swap with your hands - You must use an insulated chip removal tool to avoid a short-circuit)

You have several options to get spare BIOS chips:

What kind of hardware tools do I need?

See the hardware tools section of the developer's manual.

How do I use a null-modem cable to get coreboot debugging output over a serial port?

  • First, you'll want to set up a terminal program, e.g. minicom correctly.
$ minicom -s
 -> Serial port setup
 -> Press A and enter your COM device (ttyS0 or ttyS1 or ttyUSB0, depending on your COM port)
 -> Press E and choose "115200 8N1" (default)
 -> Disable Hardware and Software Flow Control (via F and G)
 -> Press enter to leave the menu
 -> Save setup as..
 ->   Enter "lb"
 -> Exit from minicom
  • From now on, you can start minicom with the obove settings simply by typing:
$ minicom -o lb

What documentation do I need?

As much documentation as you can possibly get your hands on. At minimum, you will need the docs for the chipset.

There have been reports of people getting coreboot working by booting with the OEM BIOS. Then, they would read the static contents of the PCI config registers after boot. coreboot is then built to match the static contents read from the PCI config registers.

The problem with this approach is that chipsets generally require dynamic vs static configuration values during their initialization. The configuration register contents will change from one stage of initialization to the next. Since the contents of the registers read is only the final state of the configuration registers, the chipset won't be properly initialized if these are the only configuration values used.

Getting a mainboard up without chipset docs can be a very long and involved process.

What if my chipset docs are covered by an NDA?

If the documentation for your chipset covered by a NDA with no source release agreement, you won't be able to release your code back to the coreboot project in general, or you will violate the GPL. Many vendors accept releasing the source code, produced after reading such specs, while they don't allow the specs themselves to be revealed. Also, you can offer them the opportunity to review your code, before releasing it to the public.

Why is the code so complicated and what can I do to make it easier?

The reason is the complexity of the problem. We support a lot of hardware, and a given chip on a given board will most likely not be configured quite the same as the same chip on some other board. To help make code navigation easier, pick a target and build that target. Then, in the build directory, type make tags or make etags to get your favorite tags file.

How do I contribute my changes?

Please carefully read the Development Guidelines for more information.

How do I identify the BIOS chip on my mainboard?

Please see [1].

How do I (re-)flash the BIOS?

Out of mainboard BIOS (re)flash

If the BIOS chip is socketed, it can be removed and flashed in a rom/flash burner and quickly re-installed.

You have the option of using the external programmers supported by flashrom or some other external programmer which comes with its own software. Depending on the flash chip type, various options exist. For older parallel flash chips, some of these burners cost $700 and more plus they complete a flash in 30 seconds (like the Conitec Galep V), but if you are willing to wait 5 minutes for a flash and manually set DIP switches, the Enhanced Willem Universal Programmer will do the job for only $40-60 USD. There are several models of the Willem Programmer, each supporting many chips, but not all, so be sure to get one that supports your BIOS chip. You could also use the Paraflasher which is a really low-cost programmer with parts sold for $20 or less. The flashrom wiki has a list of hardware you can use for programming.

If your chip is PLCC, you will also need the push pin trick or a PLCC chip extractor/puller or just thread nylon string under the PLCC chip from corner to corner and yank up it straight up. Read more about chip extraction in the developer manual.

Inside mainboard BIOS (re)flash

Download the appropriate flash update utility. Build the coreboot image as explained above and use the flash update utility to update the BIOS. Be warned that not all update utilities allow you to load your own BIOS image. NOTE: Many vendor specific flash utilities refuse to write "foreign" BIOS images, such as coreboot.

Therefore we suggest that you use the universal flash utility called flashrom which was developed and improved by many coreboot developers, and it works under Linux/*BSD/MacOSX/Solaris/DOS.

Example: 

bash$ sudo ./flashrom -V
flashrom v0.9.2-r1000 on Linux 2.6.34-rc7-git5 (x86_64), built with libpci 3.1.7, GCC 4.4.3
flashrom is free software, get the source code at http://www.flashrom.org

No coreboot table found.
Found chipset "Intel ICH9", enabling flash write... OK.
This chipset supports the following protocols: FWH,SPI.
Calibrating delay loop... 663M loops per second, 100 myus = 199 us. OK.
Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000.
No operations were specified.

Alternatively you could either use the DOS uniflash utility, or use its source code, which is also available for download from the uniflash site (in Turbo Pascal 7) as a reference for adding support for your flash chip to flashrom. Uniflash supports a lot of different flash chips, and chip interfaces, but so far SPI support is only present in flashrom. You can use flashrom and uniflash for PCI expansion card flashing, such as on RTL8139 Ethernet card (32pin DIL), which allows flashing of your BIOS chip on the NIC if manufacturer provides the circuitry. Please note that flashrom and uniflash support different cards and you should check which utility supports the programmer hardware you own.

Another tool which runs in linux is ctflasher, but it is not maintained anymore and might not work with current Linux kernels.


BIOS Savior RD1

BIOS Savior RD1

There are some posts about the BIOS Savior RD1 that suggest its integrated flash device is of low quality; it may take 10 or more flash programming attempts to get a good update to the RD1 flash device. As a result, the following steps have proven to be successful while using the RD1:

  • Step 1 - While the system is powered down, remove the original BIOS device from the mainboard and insert it into the RD1's socket.
  • Step 2 - Insert the RD1 into the mainboard's flash BIOS socket.
  • Step 3 - Boot the system with the RD1 set to boot from the original flash device from the mainboard.
  • Step 4 - Program the original BIOS image (or other known good BIOS image) into the RD1's integrated flash device. Do this as many times as needed until the device is properly programmed and the system boots corectly from the RD1's integrated flash device. Be sure to check the settings on the RD1 so that the proper flash device is now being programmed. If the RD1 is not set correctly the working BIOS image will be erased and the system will not boot!
  • Step 5 - Program the test BIOS image (usually coreboot images are among this group) into the original flash device from the mainboard. The original BIOS device usually programs OK on the first attempt. Be sure to check the settings again on the RD1 so that the proper flash device is being programmed!


The RD1 has been used in the above fashion with great success on the Tyan S2885 mainboard. Unfortunately the RD1 does not work on the nVidia CK8-04 CRB mainboard. The CK8-04 CRB may require a flash device that the RD1 does not support.

The RD1 has worked well as a "do nothing" adapter that allows swapping the BIOS flash device between a flash burner and a mainboard without any wear to the mainboard's BIOS socket.

Can I do any serious damage mucking around with this stuff?

Any time you stick your hand into an open machine while the power is on, you're risking life and limb. That said, there are also some other not-so-nice things that can happen if you mess up (not that we would know).

  • Incorrect insertion of the flash (1 casualty)
  • Incorrect jumper settings (1 casualty)
  • Aggressive and/or inappropriate use of metal objects such as screwdrivers (2 casualties)
  • Miscellaneous miswirings and mishandlings (3+ casualties)

remember: make sure your important data is on a disconnected drive while you experiment.

A note on electrostatic discharge (ESD) and ESD protection (thanks to Bari Ari)

ESD can damage disk drives, boards, DoC's and other parts. The majority of the time, ESD events cause the component to degrade, but not fail testing procedures, resulting in failure at a later date. Because components do not fail immediately, technicians often underestimate the cost of not using ESD prevention measures. Provide at minimum some ESD protection by wearing an antistatic wrist strap attached to the chassis ground on your system when handling parts.

Always handle boards carefully. They can be extremely sensitive to ESD. Hold boards only by their edges. After removing a board from its protective wrapper or from the system, place it component side up on a grounded, static free surface. Use a conductive foam pad if available. Do not slide the board over any surface.

To further reduce the chances of ESD, you should create an ESD safe workstation that includes at minimum:

  • Conductive rubber mat, with a lead wire that can be connected to a metal surface to create a ground.
  • ESD wrist strap, which has a resistor inside the strap and a lead wire that can be connected to a metal surface as a ground. The grounding wire on the wrist strap should have between 1 and 10 Megaohms of resistance. The resistor should protect you in case you come in contact with a voltage source. If the resistor is bad or not included, the wrist strap is useless. An accidental shock could be serious and even deadly!
  • Table or workspace that is clean, clear of dust, and away from electrical machinery or other equipment that generates electrical currents.

The idea is to ensure that all components you are going to interact with have the same charge. By connecting everything to the computer case, you ensure that the components of the case, the chair, and your body all have the same charge. If every object has the same charge, the electrons will not jump from one object to another minimizing the risk of ESD damage.

What is a PIRQ table?

There's a good description of the BIOS implementation of the PIRQ in the red PCI book, and here's a description of the $PIR data structure.

coreboot saves the $PIR data structure between 0xf0000 & 0x100000. Search for $PIR and then save it before copying over the BIOS.

See also the ADLO README for more information.

How do I set up etherboot with coreboot?

Note from Ron: I have edited this somewhat to remove Geode-specific items. 

Christer Weinigel writes: 
To: rminnich@lanl.gov
Cc: linuxbios@lanl.gov
Subject: Re: LinuxBIOS + Etherboot HOWTO?

I had some trouble using LinuxBIOS + etherboot... 

My bad, I messed up and used mkelfImage-1.6 that I got from ftp.lnxi.com, when I realized that I ought to use the one from freebios/util everything started working. 

Here's what I did to get LinuxBIOS + Etherboot loading and booting a Linux kernel using TFTP. 

  /Christer 

Get etherboot-5.0 from the CVS tree on etherboot.sourceforge.net. 

Modify etherboot-5.0/src/Config, comment out: 

   # BIOS select don't change unless you know what you are doing
   #CFLAGS32+=     -DPCBIOS

and uncomment the following: 

   # Options to make a version of Etherboot that will work under linuxBIOS.
   CFLAGS32+= -DLINUXBIOS -DCONFIG_TSC_CURRTICKS  -DCONSOLE_SERIAL \
              -DCOMCONSOLE=0x3f8 -DCOMPRESERVE -DCONFIG_PCI_DIRECT -DELF_IMAGE 

Compile Etherboot to make an elf file for your ethernet card: 

    make bin32/natsemi.elf

Compile and install mkelfImage from freebios/util/mkelfImage. 

Create a bootimage to put on your TFTP server: 

   mkelfImage --command-line="root=/dev/hda2 console=ttyS0,38400" \
              --kernel vmlinux -o /tftpboot/kernel

Finally, make sure that your BOOT/DCHP server is answering and that the TFTP server is active. 

Tell LinuxBIOS to boot an elf Image, and tell LinuxBIOS where it is: 

   option USE_ELF_BOOT=1

I have placed natsemi.elf in the first 64k of my BIOS flash chip, and LinuxBIOS in the second 64k. 

   insmod bios.o
   dd if=natsemi.elf of=/dev/bios bs=64k
   dd if=linuxbios.rom of=/dev/bios bs=64k seek=1

Finally boot LinuxBIOS.

How do I set GEODE graphics and video?

There is no Geode graphics support in coreboot. Install the Geode framebuffer driver for console graphics and the X driver for X support on your Geode Linux image. Current kernel and X distributions contain the required drivers. Until the driver loads there is only serial console output.

Driver source:

2.6.23 kernel framebuffer driver

X.org driver

How do I set up testbios?

Please read the testbios FAQ.

/usr/sbin/iasl: Command not found

If you see this error, you have to install iasl, Intel's ASL Optimizing Compiler:

How can I write to POSTcard port 0x80 from userspace?

This might be useful in some situations, and to output a number to a POST card: 

printf "\001" | dd bs=1 seek=128 of=/dev/port

or using iotools: 

iotools io_write8 0x80 0x42

In case of linux commands above do output to POST card, but the value is immediately replaced by 0x00 due to io_delay. Further explanations can be found on kernel mailinglist archive


In DOS (not Windows XP) use: 

mov al, 42; out al, 80h

To output 42 type 

o 80 42

in DOS debug.exe.

When using LPT (parallel port) POST card - write to port assigned to parallel port, eg. 0x3BC, 0x378, 0x278. Some SuperIOs/EmbeddedControllers will decode 0x80 like ENE KB926

Is coreboot applying x86 microcode patches?

And if yes, can they be modified?

Answer: Yes, coreboot is applying microcode patches on AMD and Intel CPUs. However, this field is little documented, so coreboot uses only unmodified, vendor-provided microcode. Few people think, that system design can seriously be improved by modifications here ( �Code patches mostly disable erraneous functions and opcodes).

How can I retrieve a good video BIOS?

Note: If you are following these instructions to build coreboot for your motherboard, this is only necessary if you have a motherboard with an embedded VGA card. If your VGA is a PCI / PCI-Express add-on card, coreboot will find and run the ROM by itself.

See VGA_support for the details.


Errors

ERROR: Not enough MTRRs available!

There are 8 dynamic MTRRs available on x86.

This message tells you that there's an error with PCI device resources.

It might be an error in the PCI handling code or the devicetree.

Can I put coreboot into a PCI expansion ROM?

Short answer: NO.

Long answer:

There's little use in doing that, as a lots of initialization has already been done by the proprietary BIOS (or coreboot) by the time the PCI expansion ROM is executed. It won't be possible to run coreboot from a PCI expansion ROM after a proprietary BIOS has already been running for instance.

Note: The Intel ICH7 southbridge seems to allows booting from PCI ROMs (not arbitrary PCI expansion ROMs as used on graphics cards, SCSI controllers, etc.) -- maybe this should be investigated in order to check if or how it might be useful.

Obsolete FAQ items

Please see FAQ/Obsolete for (probably) obsolete FAQ items.

Retrieved from "https://www.coreboot.org/index.php?title=FAQ&oldid=33086"