Talk:FOSDEM 2010: Difference between revisions
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=== Peter technical details === | === Peter technical details === | ||
* modern pc architecture | * modern pc architecture | ||
* interrupts | * CPU i/o (ports/memory) | ||
* registers in hardware, "ISA" and PCI | |||
* NVRAM | |||
* interrupts | |||
* PIC APIC PIRQ/MP tables [[Media:ApicSystem.svg]] | |||
* ram init | * ram init | ||
* cache-as-ram | * cache-as-ram |
Latest revision as of 05:06, 18 January 2010
Peter intro
- what is coreboot - history - motivation
- payloads and compression
- v2/v3
- cbfs
- other software in same and related fields
- sibling projects and utilities: seabios serialice coreinfo bayou libpayload buildrom mkelfImage nvramtool superiotool inteltool msrtool flashrom
- security issues
Peter technical details
- modern pc architecture
- CPU i/o (ports/memory)
- registers in hardware, "ISA" and PCI
- NVRAM
- interrupts
- PIC APIC PIRQ/MP tables Media:ApicSystem.svg
- ram init
- cache-as-ram
- gcc vs. romcc
- real mode, protected mode, system management mode
- mention embedded controllers and capabilities and tasks
Rudolf acpi
- what for is ACPI
- Sleep states in more detail - S1 S2 S3 S4 S5
- CPU power modes C1/C2/C3
- hardware side - PM regs
- software architecture of ACPI
- Tables in more detail
- Some tour through it acpiextract iasl
- Coreboot specific stuff - perhaps the ACPIgen
- and SSDT generation
- suspend/resume from HW point of view - memory controller stuff too
- SW flow through coreboot + ram preservation issues
Rudolf board porting
- Get to know your HW (lspci, superiotool)
- serial setup + troubles wrong OSC speeds
- GPIO setup
- watchdogs - yes ite has default on :)
- IRQ routing in ACPI? maybe some ideas...
- ACPI specific stuff for each board
- porting on supported chipset - describe the early setup for mainboard + directory content for the board
- some ideas for porting on new unsupported chipset