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| Until recently, coreboot was using a custom, "home-made" config system. For some time you can look at the [[Coreboot Options(old)|old list of options]].
| | {{#externalredirect: https://coreboot.org/status/kconfig-options.html }} |
| | |
| The new config system is [[Kconfig]] (a.k.a. "make menuconfig"), the well-known system as also used by the Linux kernel, busybox and a various other projects.
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| | |
| This is an automatically generated list of '''coreboot kconfig compile-time options'''.
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| | |
| Last update: 2010/02/09 15:05:25. (r5100)
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| {| border="0" style="font-size: smaller" | |
| |- bgcolor="#6699dd"
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| ! align="left" | Option
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| ! align="left" | Source
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| ! align="left" | Format
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| ! align="left" | Short Description
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| ! align="left" | Description
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: General setup || || || ||
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| |- bgcolor="#eeeeee"
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| | EXPERT || toplevel || bool || Expert mode ||
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| This allows you to select certain advanced configuration options.
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| Warning: Only enable this option if you really know what you are
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| doing! You have been warned!
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| |- bgcolor="#eeeeee"
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| | LOCALVERSION || toplevel || string || Local version string ||
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| Append an extra string to the end of the coreboot version.
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| | |
| This can be useful if, for instance, you want to append the
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| respective board's hostname or some other identifying string to
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| the coreboot version number, so that you can easily distinguish
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| boot logs of different boards from each other.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Mainboard || || || ||
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| |- bgcolor="#eeeeee"
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| | BOARD_ROMSIZE_KB_4096 || mainboard || bool || ROM chip size ||
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| Select the size of the ROM chip you intend to flash coreboot on.
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| The build system will take care of creating a coreboot.rom file
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| of the matching size.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
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| Choose this option if you have a 128 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
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| Choose this option if you have a 256 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
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| Choose this option if you have a 512 KB ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
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| Choose this option if you have a 1024 KB (1 MB) ROM chip.
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
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| Choose this option if you have a 2048 KB (2 MB) ROM chip.
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| ||
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| |- bgcolor="#eeeeee"
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| | COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
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| Choose this option if you have a 4096 KB (4 MB) ROM chip.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Chipset || || || ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || CPU ||
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| |- bgcolor="#eeeeee"
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| | SMP || cpu || bool || ||
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| This option is used to enable certain functions to make coreboot
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| work correctly on symmetric multi processor (SMP) systems.
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| |- bgcolor="#eeeeee"
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| | VAR_MTRR_HOLE || cpu || bool || ||
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| Unset this if you don't want the MTRR code to use
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| subtractive MTRRs
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Northbridge ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Southbridge ||
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: AMD Geode GX1 video support || || || ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Super I/O ||
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| |- bgcolor="#eeeeee"
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| | || || (comment) || || Devices ||
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| |- bgcolor="#eeeeee"
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| | VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
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| Allow bridges to set up legacy decoding ranges for VGA. Don't disable
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| this unless you're sure you don't want the briges setup for VGA.
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| |- bgcolor="#eeeeee"
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| | VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
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| Execute VGA option ROMs, if found. This is required to enable
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| PCI/AGP/PCI-E video cards.
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| |- bgcolor="#eeeeee"
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| | PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
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| Execute non-VGA PCI option ROMs, if found.
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| Examples include IDE/SATA controller option ROMs and option ROMs
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| for network cards (NICs).
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| |- bgcolor="#eeeeee"
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| | PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Real mode ||
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| If you select this option, PCI option ROMs will be executed
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| natively on the CPU in real mode. No CPU emulation is involved,
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| so this is the fastest, but also the least secure option.
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| (only works on x86/x64 systems)
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| ||
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| |- bgcolor="#eeeeee"
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| | PCI_OPTION_ROM_RUN_X86EMU || devices || bool || x86emu ||
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| If you select this option, the x86emu CPU emulator will be used to
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| execute PCI option ROMs.
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| When choosing this option, x86emu will pass through all hardware
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| accesses to memory and IO devices to the underlying memory and IO
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| addresses. While this option prevents option ROMs from doing dirty
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| tricks with the CPU (such as installing SMM modules or hypervisors),
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| they can still access all devices in the system.
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| Choosing x86emu, option ROM execution is slower than native execution
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| in real mode, but faster than the full system emulation YABEL
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| This is the default choice for non-x86 systems.
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| |- bgcolor="#eeeeee"
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| | PCI_OPTION_ROM_RUN_YABEL || devices || bool || YABEL ||
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| If you select this option, the YABEL system emulator will be used to
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| execute PCI option ROMs.
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| YABEL consists of two parts: It uses x86emu for the CPU emulation and
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| additionally provides a PC system emulation that filters bad device and
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| memory access (such as PCI config space access to other devices than the
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| initialized one).
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| This option best prevents option ROMs from doing dirty tricks with the
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| system (such as installing SMM modules or hypervisors), but it is also
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| significantly slower than the other option ROM initialization methods.
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| |- bgcolor="#eeeeee"
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| | YABEL_DEBUG_FLAGS || devices || hex || Hex value for YABEL debug flags ||
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| See debug.h for values 0 is no debug output, 0x31ff is _verbose_.
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Console options || || || ||
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
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| Send coreboot debug output to a serial port console.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
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| Serial console on COM1/ttyS0 at I/O port 0x3f8.
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| ||
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
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| Serial console on COM2/ttyS1 at I/O port 0x2f8.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
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| Serial console on COM3/ttyS2 at I/O port 0x3e8.
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| ||
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
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| Serial console on COM4/ttyS3 at I/O port 0x2e8.
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| |- bgcolor="#eeeeee"
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| | TTYS0_BASE || console || hex || ||
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| Map the COM port names to the respective I/O port.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_115200 || console || bool || 115200 ||
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| Set serial port Baud rate to 115200.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_57600 || console || bool || 57600 ||
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| Set serial port Baud rate to 57600.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_38400 || console || bool || 38400 ||
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| Set serial port Baud rate to 38400.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_19200 || console || bool || 19200 ||
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| Set serial port Baud rate to 19200.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_SERIAL_9600 || console || bool || 9600 ||
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| Set serial port Baud rate to 9600.
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| |- bgcolor="#eeeeee"
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| | TTYS0_BAUD || console || int || ||
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| Map the Baud rates to an integer.
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| |- bgcolor="#eeeeee"
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| | SERIAL_POST || console || bool || Show POST codes on the serial port console ||
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| If enabled, coreboot will additionally print POST codes (which are
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| usually displayed using a so-called "POST card" ISA/PCI/PCI-E
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| device) on the serial console.
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| |- bgcolor="#eeeeee"
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| | USBDEBUG_DIRECT || console || bool || USB 2.0 EHCI debug dongle support ||
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| This option allows you to use a so-called USB EHCI Debug device
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| to retrieve the coreboot debug messages (instead, or in addition
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| to, a serial port).
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| This feature is NOT supported on all chipsets in coreboot!
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| It also requires a USB2 controller which supports the EHCI
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| Debug Port capability. Controllers which are known to work:
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| * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
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| * 8086:24cd Intel ICH4/ICH4-M
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| * 8086:24dd Intel ICH5
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| * 8086:265c Intel ICH6
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| * 8086:268c Intel 631xESB/632xESB/3100
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| * 8086:27cc Intel ICH7
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| * 8086:2836 Intel ICH8
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| * 8086:283a Intel ICH8
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| * 8086:293a Intel ICH9
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| * 10de:0088 NVIDIA MCP2A
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| * 10de:005b NVIDIA CK804
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| * 10de:026e NVIDIA MCP51
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| * 10de:036d NVIDIA MCP55
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| * 10de:03f2 NVIDIA MCP61
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| * 1002:4386 ATI/AMD SB600
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| * 1106:3104 VIA VX800
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| See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
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| |- bgcolor="#eeeeee"
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| | CONSOLE_VGA_ONBOARD_AT_FIRST || console || bool || Use onboard VGA as primary video device ||
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| If not selected, the last adapter found will be used.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
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| Way too many details.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
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| Debug-level messages.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
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| Informational messages.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
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| Normal but significant conditions.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
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| Warning conditions.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
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| Error conditions.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
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| Critical conditions.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
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| Action must be taken immediately.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
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| System is unusable.
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| |- bgcolor="#eeeeee"
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| | MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||
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| Map the log level config names to an integer.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
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| Way too many details.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
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| Debug-level messages.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
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| Informational messages.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
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| Normal but significant conditions.
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| ||
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
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| Warning conditions.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
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| Error conditions.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
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| Critical conditions.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
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| Action must be taken immediately.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
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| System is unusable.
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| |- bgcolor="#eeeeee"
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| | DEFAULT_CONSOLE_LOGLEVEL || console || int || ||
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| Map the log level config names to an integer.
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| |- bgcolor="#eeeeee"
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| | HAVE_OPTION_TABLE || toplevel || bool || ||
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| This variable specifies whether a given board has a cmos.layout
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| file containing NVRAM/CMOS bit definitions.
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| It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
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| |- bgcolor="#eeeeee"
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| | VGA || toplevel || bool || ||
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| Build board-specific VGA code.
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| |- bgcolor="#eeeeee"
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| | GFXUMA || toplevel || bool || ||
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| Enable Unified Memory Architecture for graphics.
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| |- bgcolor="#eeeeee"
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| | HAVE_LOW_TABLES || toplevel || bool || ||
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| This Option is unused in the code. Since two boards try to set it to
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| 'n', they may be broken. We either need to make the option useful or
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| get rid of it. The broken boards are:
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| asus/m2v-mx_se
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| supermicro/h8dme
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| ||
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| |- bgcolor="#eeeeee"
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| | HAVE_HIGH_TABLES || toplevel || bool || ||
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| This variable specifies whether a given northbridge has high table
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| support.
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| It is set in northbridge/*/Kconfig.
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| Whether or not the high tables are actually written by coreboot is
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| configurable by the user via WRITE_HIGH_TABLES.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | HAVE_ACPI_TABLES || toplevel || bool || ||
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| This variable specifies whether a given board has ACPI table support.
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| It is usually set in mainboard/*/Kconfig.
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| Whether or not the ACPI tables are actually generated by coreboot
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| is configurable by the user via GENERATE_ACPI_TABLES.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | HAVE_MP_TABLE || toplevel || bool || ||
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| This variable specifies whether a given board has MP table support.
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| It is usually set in mainboard/*/Kconfig.
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| Whether or not the MP table is actually generated by coreboot
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| is configurable by the user via GENERATE_MP_TABLE.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | HAVE_PIRQ_TABLE || toplevel || bool || ||
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| This variable specifies whether a given board has PIRQ table support.
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| It is usually set in mainboard/*/Kconfig.
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| Whether or not the PIRQ table is actually generated by coreboot
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| is configurable by the user via GENERATE_PIRQ_TABLE.
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| | |
| ||
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: System tables || || || ||
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| |- bgcolor="#eeeeee"
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| | GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
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| Generate ACPI tables for this board.
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| If unsure, say Y.
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| ||
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| |- bgcolor="#eeeeee"
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| | GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
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| Generate an MP table (conforming to the Intel MultiProcessor
| |
| specification 1.4) for this board.
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| If unsure, say Y.
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| | |
| ||
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| |- bgcolor="#eeeeee"
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| | GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
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| Generate a PIRQ table for this board.
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| | |
| If unsure, say Y.
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| | |
| ||
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| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Payload || || || ||
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| |- bgcolor="#eeeeee"
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| | PAYLOAD_NONE || toplevel || bool || None ||
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| Select this option if you want to create an "empty" coreboot
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| ROM image for a certain mainboard, i.e. a coreboot ROM image
| |
| which does not yet contain a payload.
| |
| | |
| For such an image to be useful, you have to use 'cbfstool'
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| to add a payload to the ROM image later.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
| |
| Select this option if you have a payload image (an ELF file)
| |
| which coreboot should run as soon as the basic hardware
| |
| initialization is completed.
| |
| | |
| You will be able to specify the location and file name of the
| |
| payload image later.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | FALLBACK_PAYLOAD_FILE || toplevel || string || Payload path and filename ||
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| The path and filename of the ELF executable file to use as payload.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
| |
| In order to reduce the size payloads take up in the ROM chip
| |
| coreboot can compress them using the LZMA algorithm.
| |
| | |
| ||
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| | |
| |- bgcolor="#6699dd"
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| ! align="left" | Menu: VGA BIOS || || || ||
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| |- bgcolor="#eeeeee"
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| | VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
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| Select this option if you have a VGA BIOS image that you would
| |
| like to add to your ROM.
| |
| | |
| You will be able to specify the location and file name of the
| |
| image later.
| |
| | |
| ||
| |
| |- bgcolor="#eeeeee"
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| | FALLBACK_VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
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| The path and filename of the file to use as VGA BIOS.
| |
| | |
| ||
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| |- bgcolor="#eeeeee"
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| | FALLBACK_VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
| |
| The comma-separated PCI vendor and device ID that would associate
| |
| your VGA BIOS to your video card.
| |
| | |
| Example: 1106,3230
| |
| | |
| In the above example 1106 is the PCI vendor ID (in hex, but without
| |
| the "0x" prefix) and 3230 specifies the PCI device ID of the
| |
| video card (also in hex, without "0x" prefix).
| |
| | |
| ||
| |
| | |
| |- bgcolor="#6699dd"
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| ! align="left" | Menu: Debugging || || || ||
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| |- bgcolor="#eeeeee"
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| | GDB_STUB || toplevel || bool || GDB debugging support ||
| |
| If enabled, you will be able to set breakpoints for gdb debugging.
| |
| See src/arch/i386/lib/c_start.S for details.
| |
| | |
| ||
| |
| | |
| |}
| |