Developer Manual: Difference between revisions
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(→Serial output and the Super I/O: Some text and photos.) |
(→Serial output and the Super I/O: Some hints.) |
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Image:Ite it8705f.jpg|ITE IT8705F Super I/O. | Image:Ite it8705f.jpg|ITE IT8705F Super I/O. | ||
</gallery> | </gallery> | ||
The steps for adding support for a new Super I/O chip are: | |||
* Add a directory src/superio/''vendor''/''device'' (e.g. src/superio/winbond/w83627ehg). | |||
* In that directory, add a file ''device''_early_serial.c (e.g. w83627ehg_early_serial.c). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even ''before'' the RAM is initialized, thus is useful/required for debugging the RAM initialization process. | |||
* In this file you now declare a function ''device''_enable_serial() which enables the requested serial port. Example: | |||
static void w83627ehg_enable_serial(device_t dev, unsigned int iobase) | |||
{ | |||
pnp_enter_ext_func_mode(dev); | |||
pnp_set_logical_device(dev); | |||
pnp_set_enable(dev, 0); | |||
pnp_set_iobase(dev, PNP_IDX_IO0, iobase); | |||
pnp_set_enable(dev, 1); | |||
pnp_exit_ext_func_mode(dev); | |||
} | |||
* ... | |||
== Northbridge == | == Northbridge == |
Revision as of 22:33, 29 May 2007
This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. |
This is work in progress!
Introduction
Hardware Overview
LinuxBIOS Overview
Serial output and the Super I/O
The Super I/O is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard (e.g. COM1, COM2). This chip usually the first thing you'll want to support, as it's required to get serial debugging output from the mainboard (via a null-modem cable and the proper software, e.g. minicom).
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Winbond W83977EF Super I/O.
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ITE IT8705F Super I/O.
The steps for adding support for a new Super I/O chip are:
- Add a directory src/superio/vendor/device (e.g. src/superio/winbond/w83627ehg).
- In that directory, add a file device_early_serial.c (e.g. w83627ehg_early_serial.c). This file will be responsible to setup a serial port on the mainboard so that you can get serial debugging output. This will work even before the RAM is initialized, thus is useful/required for debugging the RAM initialization process.
- In this file you now declare a function device_enable_serial() which enables the requested serial port. Example:
static void w83627ehg_enable_serial(device_t dev, unsigned int iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
- ...
Northbridge
RAM init
Resources:
- Understanding DDR Serial Presence Detect (SPD) Table
- Micron 512 MB SDRAM Datasheet (PDF) -- contains some helpful explanations