User:Hailfinger: Difference between revisions
Jump to navigation
Jump to search
Hailfinger (talk | contribs) No edit summary |
Hailfinger (talk | contribs) No edit summary |
||
| Line 2: | Line 2: | ||
My LinuxBIOS/coreboot-related interests and contributions are | My LinuxBIOS/coreboot-related interests and contributions are | ||
* flashrom SPI support (I wrote all SPI support code) and generic flash chip support | * flashrom architecture, SPI support (I wrote all SPI support code), external flasher infrastructure and generic flash chip support | ||
* superiotool support | * superiotool support | ||
* coreboot v3 design and restructuring work as well as board support. | * coreboot v3 design and restructuring work as well as board support | ||
* porting coreboot v3 code to v2. | |||
I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. | I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. Updating v2 to use as much v3 code as possible is one of the ways to achieve this goal. | ||
Legal disclaimer: My opinions do not | Legal disclaimer: My opinions do not represent the opinions of the coreboot project. | ||
Revision as of 14:55, 22 June 2009
My LinuxBIOS/coreboot-related interests and contributions are
- flashrom architecture, SPI support (I wrote all SPI support code), external flasher infrastructure and generic flash chip support
- superiotool support
- coreboot v3 design and restructuring work as well as board support
- porting coreboot v3 code to v2.
I consider coreboot v2 to be a legacy codebase and hope we can one day support all boards in v3 which are working under v2. Updating v2 to use as much v3 code as possible is one of the ways to achieve this goal.
Legal disclaimer: My opinions do not represent the opinions of the coreboot project.