Nvramtool

nvramtool (previously known as lxbios) is a utility for reading/writing coreboot parameters and displaying information from the coreboot table in CMOS/NVRAM.

The program works only on x86-based Linux systems that use coreboot.

Installation

Manual Installation

$ svn co svn://coreboot.org/repos/trunk/util/nvramtool
$ cd nvramtool
$ make
$ sudo make install  (optional)

Debian

$ sudo aptitude install nvramtool

Using nvramtool

Running nvramtool on a system running coreboot would yield a result like this:

 # ./nvramtool -a
 boot_option = Fallback
 last_boot = Fallback
 ECC_memory = Disable
 baud_rate = 115200
 hw_scrubber = Enable
 interleave_chip_selects = Enable
 max_mem_clock = 100Mhz
 dual_core = Enable
 power_on_after_fail = Enable
 debug_level = Spew
 boot_first = HDD
 boot_second = Network
 boot_third = Floppy
 boot_index = 0xe
 boot_countdown = 0xfa
 slow_cpu = off
 nmi = Enable
 iommu = Enable
 nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.

Commonly used CMOS/NVRAM options

coreboot v2

Option	Used in	Comment	Possible values
baud_rate	src/pc80/serial.c	The serial port BAUD rate setup by coreboot.	115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200
debug_level	src/console/console.c	The coreboot debugging level.	Notice, Info, Debug, Spew
ECC_memory	src/northbridge/intel/e7520/raminit.c src/northbridge/intel/e7525/raminit.c src/northbridge/amd/amdk8/raminit.c src/northbridge/amd/amdk8/raminit_f.c		Enable, Disable
interleave_chip_selects	src/northbridge/amd/amdk8/raminit.c src/northbridge/amd/amdk8/raminit_f.c		Enable, Disable
max_mem_clock	src/northbridge/amd/amdk8/raminit.c src/northbridge/amd/amdk8/raminit_f.c		mainboard-dependent
dual_core	src/cpu/amd/model_fxx/init_cpus.c src/cpu/amd/dualcore/dualcore.c src/northbridge/amd/amdk8/coherent_ht.c src/cpu/amd/dualcore/amd_sibling.c src/northbridge/amd/amdk8/northbridge.c		Enable, Disable
quad_core	src/cpu/amd/quadcore/quadcore.c src/cpu/amd/model_10xxx/init_cpus.c src/cpu/amd/quadcore/amd_sibling.c src/northbridge/amd/amdfam10/northbridge.c
power_on_after_fail	src/southbridge/amd/sb600/sb600_sm.c src/southbridge/amd/amd8111/amd8111_acpi.c src/southbridge/nvidia/ck804/ck804_lpc.c src/southbridge/nvidia/mcp55/mcp55_lpc.c src/southbridge/intel/i82801ca/i82801ca_lpc.c src/southbridge/intel/esb6300/esb6300_lpc.c src/southbridge/intel/i82801er/i82801er_lpc.c src/southbridge/intel/i3100/i3100_lpc.c src/southbridge/sis/sis966/sis966_lpc.c src/superio/winbond/w83627ehg/superio.c src/superio/winbond/w83627hf/superio.c		Enable, Disable
slow_cpu	src/southbridge/amd/amd8111/amd8111_acpi.c src/southbridge/nvidia/ck804/ck804_lpc.c src/southbridge/nvidia/mcp55/mcp55_lpc.c src/southbridge/sis/sis966/sis966_lpc.c		off, 87.5%, 75.0%, 62.5%, 50.0%, 37.5%, 25.0%, 12.5%
nmi	src/southbridge/amd/sb600/sb600_sm.c src/southbridge/amd/amd8111/amd8111_acpi.c src/southbridge/amd/amd8111/amd8111_lpc.c src/southbridge/amd/amd8131/amd8131_bridge.c src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c src/southbridge/nvidia/ck804/ck804_lpc.c src/southbridge/nvidia/mcp55/mcp55_lpc.c src/southbridge/intel/i82801ca/i82801ca_lpc.c src/southbridge/intel/esb6300/esb6300_lpc.c src/southbridge/intel/i82801er/i82801er_lpc.c src/southbridge/intel/pxhd/pxhd_bridge.c src/southbridge/intel/i82801xx/i82801xx_lpc.c src/southbridge/intel/i3100/i3100_lpc.c src/southbridge/intel/i82801dbm/i82801dbm_lpc.c src/southbridge/sis/sis966/sis966_lpc.c		Enable, Disable
pxhd_bus_speed_100	src/southbridge/intel/pxhd/pxhd_bridge.c
hw_scrubber	src/cpu/amd/model_fxx/model_fxx_init.c
hyper_threading	src/cpu/intel/hyperthreading/intel_sibling.c
iommu	src/northbridge/amd/amdk8/misc_control.c src/northbridge/amd/amdfam10/misc_control.c		Enable, Disable

FILO 0.6

Option	Used in	Comment	Possible values
boot_devices	main/grub/grub.c

Etherboot 5.4.2

Option	Used in	Comment	Possible values
last_boot	src/firmware/linuxbios/linuxbios.c
boot_countdown	src/firmware/linuxbios/linuxbios.c
boot_index	src/firmware/linuxbios/linuxbios.c
boot_first	src/firmware/linuxbios/linuxbios.c
boot_second	src/firmware/linuxbios/linuxbios.c
boot_third	src/firmware/linuxbios/linuxbios.c

Things to know

1. coreboot will ignore the CMOS table if the checksum is incorrect, and will fallback to its hardcoded defaults.
2. coreboot does not initialize the CMOS/NVRAM to default values. In other words, until you set values with nvramtool, your CMOS table will have an incorrect checksum, and will simply be ignored.
3. Not all of the fields that nvramtool can set are used by coreboot on every mainboard.
4. Some of the fields are used by payloads - for instance all the fields that start with 'boot_' in the list above. FILO and Etherboot are two examples of bootloaders parsing NVRAM values (See their pages for a list of known variables)

Old websites

The nvramtool tool is now maintained by the coreboot developers and this page is the main website of nvramtool. For reference, the following websites were previously used, but are now deprecated:

• http://www.llnl.gov/linux/lxbios/lxbios.html (dead)
• https://computing.llnl.gov/linux/lxbios.html
• http://sourceforge.net/projects/lxbios/

This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.