Coreboot Options

This is an automatically generated list of coreboot compile-time options.

Last update: 2010/12/11 17:04:28. (r6168)

Option	Source	Format	Short Description	Description
Menu: General setup
EXPERT	toplevel	bool	Expert mode	This allows you to select certain advanced configuration options. Warning: Only enable this option if you really know what you are doing! You have been warned!
LOCALVERSION	toplevel	string	Local version string	Append an extra string to the end of the coreboot version. This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.
CBFS_PREFIX	toplevel	string	CBFS prefix to use	Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.
CBFS_PREFIX	toplevel	string	Compiler	This option allows you to select the compiler used for building coreboot.
SCANBUILD_ENABLE	toplevel	bool	Build with scan-build for static analysis	Changes the build process to scan-build is used. Requires scan-build in path.
SCANBUILD_REPORT_LOCATION	toplevel	string	Directory to put scan-build report in	Where the scan-build report should be stored
CCACHE	toplevel	bool	ccache	Enables the use of ccache for faster builds. Requires ccache in path.
SCONFIG_GENPARSER	toplevel	bool	Generate SCONFIG parser using flex and bison	Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l and sconfig.y. Otherwise, say N.
USE_OPTION_TABLE	toplevel	bool	Use CMOS for configuration values	Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values.
Menu: Mainboard
BOARD_OLD_REVISION	mainboard/lippert/hurricane-lx	bool	Board is old pre-3.0 revision	Look on the bottom side for a number like 406-0001-30. The last 2 digits state the PCB revision (3.0 in this example). For 2.0 or older boards choose Y, for 3.0 and newer say N. Old revision boards need a jumper shorting the power button to power on automatically. You may enable the button only after this jumper has been removed. New revision boards are not restricted in this way, and always have the power button enabled.
ONBOARD_UARTS_RS485	mainboard/lippert/hurricane-lx	bool	Switch on-board serial ports to RS485	If selected, both on-board serial ports will operate in RS485 mode instead of RS232.
ONBOARD_UARTS_RS485	mainboard/lippert/literunner-lx	bool	Switch on-board serial ports 1 & 2 to RS485	If selected, the first two on-board serial ports will operate in RS485 mode instead of RS232.
ONBOARD_IDE_SLAVE	mainboard/lippert/literunner-lx	bool	Make on-board CF socket act as Slave	If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master.
ONBOARD_UARTS_RS485	mainboard/lippert/roadrunner-lx	bool	Switch on-board serial ports to RS485	If selected, both on-board serial ports will operate in RS485 mode instead of RS232.
ONBOARD_UARTS_RS485	mainboard/lippert/spacerunner-lx	bool	Switch on-board serial ports to RS485	If selected, both on-board serial ports will operate in RS485 mode instead of RS232.
ONBOARD_IDE_SLAVE	mainboard/lippert/spacerunner-lx	bool	Make on-board SSD act as Slave	If selected, the on-board SSD will act as IDE Slave instead of Master.
BOARD_ROMSIZE_KB_4096	mainboard	bool	ROM chip size	Select the size of the ROM chip you intend to flash coreboot on. The build system will take care of creating a coreboot.rom file of the matching size.
COREBOOT_ROMSIZE_KB_128	mainboard	bool	128 KB	Choose this option if you have a 128 KB ROM chip.
COREBOOT_ROMSIZE_KB_256	mainboard	bool	256 KB	Choose this option if you have a 256 KB ROM chip.
COREBOOT_ROMSIZE_KB_512	mainboard	bool	512 KB	Choose this option if you have a 512 KB ROM chip.
COREBOOT_ROMSIZE_KB_1024	mainboard	bool	1024 KB (1 MB)	Choose this option if you have a 1024 KB (1 MB) ROM chip.
COREBOOT_ROMSIZE_KB_2048	mainboard	bool	2048 KB (2 MB)	Choose this option if you have a 2048 KB (2 MB) ROM chip.
COREBOOT_ROMSIZE_KB_4096	mainboard	bool	4096 KB (4 MB)	Choose this option if you have a 4096 KB (4 MB) ROM chip.
ENABLE_POWER_BUTTON	mainboard	bool	Enable the power button	The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds. Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.
UPDATE_IMAGE	arch/x86	bool	Update existing coreboot.rom image	If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.
Menu: Chipset
		(comment)		CPU
GEODE_VSA_FILE	cpu/amd/model_gx2	bool	Add a VSA image	Select this option if you have an AMD Geode GX2 vsa that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
VSA_FILENAME	cpu/amd/model_gx2	string	AMD Geode GX2 VSA path and filename	The path and filename of the file to use as VSA.
GEODE_VSA_FILE	cpu/amd/model_lx	bool	Add a VSA image	Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
VSA_FILENAME	cpu/amd/model_lx	string	AMD Geode LX VSA path and filename	The path and filename of the file to use as VSA.
SMP	cpu	bool		This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.
MMX	cpu	bool		Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions. ROMCC can build more efficient code if it can spill to MMX registers.
SSE	cpu	bool		Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions. ROMCC can build more efficient code if it can spill to SSE (aka XMM) registers.
SSE2	cpu	bool		Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.
VAR_MTRR_HOLE	cpu	bool		Unset this if you don't want the MTRR code to use subtractive MTRRs
		(comment)		Northbridge
Menu: HyperTransport setup
None	northbridge/amd	None	HyperTransport frequency	This option sets the maximum permissible HyperTransport link frequency. Use of this option will only limit the autodetected HT frequency. It will not (and cannot) increase the frequency beyond the autodetected limits. This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
LIMIT_HT_SPEED_AUTO	northbridge/amd	bool	HyperTransport downlink width	This option sets the maximum permissible HyperTransport downlink width. Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits. This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
LIMIT_HT_DOWN_WIDTH_16	northbridge/amd	bool	HyperTransport uplink width	This option sets the maximum permissible HyperTransport uplink width. Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits. This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
SDRAMPWR_4DIMM	northbridge/intel/i440bx	bool		This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong. If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.
OVERRIDE_CLOCK_DISABLE	northbridge/intel/i945	bool		Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.
MAXIMUM_SUPPORTED_FREQUENCY	northbridge/intel/i945	int		If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.
		(comment)		Southbridge
Menu: AMD Geode GX1 video support
		(comment)		Super I/O
		(comment)		Devices
VGA_BRIDGE_SETUP	devices	bool	Setup bridges on path to VGA adapter	Allow bridges to set up legacy decoding ranges for VGA. Don't disable this unless you're sure you don't want the briges setup for VGA.
VGA_ROM_RUN	devices	bool	Run VGA option ROMs	Execute VGA option ROMs, if found. This is required to enable PCI/AGP/PCI-E video cards.
PCI_ROM_RUN	devices	bool	Run non-VGA option ROMs	Execute non-VGA PCI option ROMs, if found. Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs).
PCI_OPTION_ROM_RUN_REALMODE	devices	bool	Native mode	If you select this option, PCI option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)
PCI_OPTION_ROM_RUN_YABEL	devices	bool	Secure mode	If you select this option, the x86emu CPU emulator will be used to execute PCI option ROMs. This option prevents option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the native option ROM initialization method. This is the default choice for non-x86 systems.
YABEL_PCI_ACCESS_OTHER_DEVICES	devices	bool	Allow option ROMs to access other devices	Per default, YABEL only allows option ROMs to access the PCI device that they are associated with. However, this causes trouble for some onboard graphics chips whose option ROM needs to reconfigure the north bridge.
YABEL_VIRTMEM_LOCATION	devices	hex	Location of YABEL's virtual memory	YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB.
YABEL_DIRECTHW	devices	bool	Direct hardware access	YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one). When choosing this option, x86emu will pass through all hardware accesses to memory and I/O devices to the underlying memory and I/O addresses. While this option prevents option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Enable this option for a good compromise between security and speed.
Menu: Generic Drivers
DRIVERS_SIL_3114	drivers	bool	Silicon Image SIL3114	It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.
Menu: Console options
CONSOLE_SERIAL8250	console	bool	Serial port console output	Send coreboot debug output to a serial port console.
CONSOLE_SERIAL_COM1	console	bool	COM1/ttyS0, I/O port 0x3f8	Serial console on COM1/ttyS0 at I/O port 0x3f8.
CONSOLE_SERIAL_COM2	console	bool	COM2/ttyS1, I/O port 0x2f8	Serial console on COM2/ttyS1 at I/O port 0x2f8.
CONSOLE_SERIAL_COM3	console	bool	COM3/ttyS2, I/O port 0x3e8	Serial console on COM3/ttyS2 at I/O port 0x3e8.
CONSOLE_SERIAL_COM4	console	bool	COM4/ttyS3, I/O port 0x2e8	Serial console on COM4/ttyS3 at I/O port 0x2e8.
TTYS0_BASE	console	hex		Map the COM port names to the respective I/O port.
CONSOLE_SERIAL_115200	console	bool	115200	Set serial port Baud rate to 115200.
CONSOLE_SERIAL_57600	console	bool	57600	Set serial port Baud rate to 57600.
CONSOLE_SERIAL_38400	console	bool	38400	Set serial port Baud rate to 38400.
CONSOLE_SERIAL_19200	console	bool	19200	Set serial port Baud rate to 19200.
CONSOLE_SERIAL_9600	console	bool	9600	Set serial port Baud rate to 9600.
TTYS0_BAUD	console	int		Map the Baud rates to an integer.
USBDEBUG	console	bool	USB 2.0 EHCI debug dongle support	This option allows you to use a so-called USB EHCI Debug device (such as the Ajays NET20DC, AMIDebug RX, or a system using the Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port). This feature is NOT supported on all chipsets in coreboot! It also requires a USB2 controller which supports the EHCI Debug Port capability. See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers. If unsure, say N.
USBDEBUG_DEFAULT_PORT	console	int	Default USB port to use as Debug Port	This option selects which physical USB port coreboot will try to use as EHCI Debug Port first (valid values are: 1-15). If coreboot doesn't detect an EHCI Debug Port dongle on this port, it will try all the other ports one after the other. This will take a few seconds of time though, and thus slow down the booting process. Hence, if you select the correct port here, you can speed up your boot time. Which USB port number (1-15) refers to which actual port on your mainboard (potentially also USB pin headers on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error.
ONBOARD_VGA_IS_PRIMARY	console	bool	Use onboard VGA as primary video device	If not selected, the last adapter found will be used.
CONSOLE_NE2K	console	bool	Network console over NE2000 compatible Ethernet adapter	Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP port 6666 on IP/MAC specified with options bellow. Use following netcat command: nc -u -l -p 6666
CONSOLE_NE2K_DST_MAC	console	string	Destination MAC address of remote system	Type in either MAC address of logging system or MAC address of the router.
CONSOLE_NE2K_DST_IP	console	string	Destination IP of logging system	This is IP adress of the system running for example netcat command to dump the packets.
CONSOLE_NE2K_SRC_IP	console	string	IP address of coreboot system	This is the IP of the coreboot system
CONSOLE_NE2K_IO_PORT	console	hex	NE2000 adapter fixed IO port address	This is the IO port address for the IO port on the card, please select some non-conflicting region, 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align)
MAXIMUM_CONSOLE_LOGLEVEL_8	console	bool	8: SPEW	Way too many details.
MAXIMUM_CONSOLE_LOGLEVEL_7	console	bool	7: DEBUG	Debug-level messages.
MAXIMUM_CONSOLE_LOGLEVEL_6	console	bool	6: INFO	Informational messages.
MAXIMUM_CONSOLE_LOGLEVEL_5	console	bool	5: NOTICE	Normal but significant conditions.
MAXIMUM_CONSOLE_LOGLEVEL_4	console	bool	4: WARNING	Warning conditions.
MAXIMUM_CONSOLE_LOGLEVEL_3	console	bool	3: ERR	Error conditions.
MAXIMUM_CONSOLE_LOGLEVEL_2	console	bool	2: CRIT	Critical conditions.
MAXIMUM_CONSOLE_LOGLEVEL_1	console	bool	1: ALERT	Action must be taken immediately.
MAXIMUM_CONSOLE_LOGLEVEL_0	console	bool	0: EMERG	System is unusable.
MAXIMUM_CONSOLE_LOGLEVEL	console	int		Map the log level config names to an integer.
DEFAULT_CONSOLE_LOGLEVEL_8	console	bool	8: SPEW	Way too many details.
DEFAULT_CONSOLE_LOGLEVEL_7	console	bool	7: DEBUG	Debug-level messages.
DEFAULT_CONSOLE_LOGLEVEL_6	console	bool	6: INFO	Informational messages.
DEFAULT_CONSOLE_LOGLEVEL_5	console	bool	5: NOTICE	Normal but significant conditions.
DEFAULT_CONSOLE_LOGLEVEL_4	console	bool	4: WARNING	Warning conditions.
DEFAULT_CONSOLE_LOGLEVEL_3	console	bool	3: ERR	Error conditions.
DEFAULT_CONSOLE_LOGLEVEL_2	console	bool	2: CRIT	Critical conditions.
DEFAULT_CONSOLE_LOGLEVEL_1	console	bool	1: ALERT	Action must be taken immediately.
DEFAULT_CONSOLE_LOGLEVEL_0	console	bool	0: EMERG	System is unusable.
DEFAULT_CONSOLE_LOGLEVEL	console	int		Map the log level config names to an integer.
SERIAL_POST	console	bool	Show POST codes on the serial port console	If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the serial console.
HAVE_HARD_RESET	toplevel	bool		This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code.
HAVE_OPTION_TABLE	toplevel	bool		This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig.
VGA	toplevel	bool		Build board-specific VGA code.
GFXUMA	toplevel	bool		Enable Unified Memory Architecture for graphics.
HAVE_ACPI_TABLES	toplevel	bool		This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig. Whether or not the ACPI tables are actually generated by coreboot is configurable by the user via GENERATE_ACPI_TABLES.
HAVE_MP_TABLE	toplevel	bool		This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.
HAVE_PIRQ_TABLE	toplevel	bool		This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.
Menu: System tables
GENERATE_ACPI_TABLES	toplevel	bool	Generate ACPI tables	Generate ACPI tables for this board. If unsure, say Y.
GENERATE_MP_TABLE	toplevel	bool	Generate an MP table	Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. If unsure, say Y.
GENERATE_PIRQ_TABLE	toplevel	bool	Generate a PIRQ table	Generate a PIRQ table for this board. If unsure, say Y.
Menu: Payload
PAYLOAD_NONE	toplevel	bool	None	Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload. For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.
PAYLOAD_ELF	toplevel	bool	An ELF executable payload	Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed. You will be able to specify the location and file name of the payload image later.
FALLBACK_PAYLOAD_FILE	toplevel	string	Payload path and filename	The path and filename of the ELF executable file to use as payload.
COMPRESSED_PAYLOAD_LZMA	toplevel	bool	Use LZMA compression for payloads	In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.
Menu: VGA BIOS
VGA_BIOS	toplevel	bool	Add a VGA BIOS image	Select this option if you have a VGA BIOS image that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
FALLBACK_VGA_BIOS_FILE	toplevel	string	VGA BIOS path and filename	The path and filename of the file to use as VGA BIOS.
FALLBACK_VGA_BIOS_ID	toplevel	string	VGA device PCI IDs	The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card. Example: 1106,3230 In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).
INTEL_MBI	toplevel	bool	Add an MBI image	Select this option if you have an Intel MBI image that you would like to add to your ROM. You will be able to specify the location and file name of the image later.
FALLBACK_MBI_FILE	toplevel	string	Intel MBI path and filename	The path and filename of the file to use as VGA BIOS.
Menu: Bootsplash
BOOTSPLASH	toplevel	bool	Show graphical bootsplash	This option shows a graphical bootsplash screen. The grapics are loaded from the CBFS file bootsplash.jpg.
FALLBACK_BOOTSPLASH_FILE	toplevel	string	Bootsplash path and filename	The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.
FRAMEBUFFER_VESA_MODE	toplevel	hex	VESA framebuffer video mode	This option sets the resolution used for the coreboot framebuffer and bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will some day make this a "choice".
COREBOOT_KEEP_FRAMEBUFFER	toplevel	bool	Keep VESA framebuffer	This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a framebuffer driver. If this option is disabled, coreboot will switch back to text mode before handing control to a payload.
Menu: Debugging
GDB_STUB	toplevel	bool	GDB debugging support	If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.
DEBUG_RAM_SETUP	toplevel	bool	Output verbose RAM init debug messages	This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_CAR	toplevel	bool	Output verbose Cache-as-RAM debug messages	This option enables additional CAR related debug messages.
DEBUG_PIRQ	toplevel	bool	Check PIRQ table consistency	If unsure, say N.
DEBUG_SMBUS	toplevel	bool	Output verbose SMBus debug messages	This option enables additional SMBus (and SPD) debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_SMI	toplevel	bool	Output verbose SMI debug messages	This option enables additional SMI related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_SMM_RELOCATION	toplevel	bool	Debug SMM relocation code	This option enables additional SMM handler relocation related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
DEBUG_MALLOC	toplevel	bool	Output verbose malloc debug messages	This option enables additional malloc related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
REALMODE_DEBUG	toplevel	bool	Enable debug messages for option ROM execution	This option enables additional x86emu related debug messages. Note: This option will increase the time to emulate a ROM. If unsure, say N.
X86EMU_DEBUG	toplevel	bool	Output verbose x86emu debug messages	This option enables additional x86emu related debug messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_JMP	toplevel	bool	Trace JMP/RETF	Print information about JMP and RETF opcodes from x86emu. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_TRACE	toplevel	bool	Trace all opcodes	Print _all_ opcodes that are executed by x86emu. WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_PNP	toplevel	bool	Log Plug&Play accesses	Print Plug And Play accesses made by option ROMs. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_DISK	toplevel	bool	Log Disk I/O	Print Disk I/O related messages. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_PMM	toplevel	bool	Log PMM	Print messages related to POST Memory Manager (PMM). Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_VBE	toplevel	bool	Debug VESA BIOS Extensions	Print messages related to VESA BIOS Extension (VBE) functions. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_INT10	toplevel	bool	Redirect INT10 output to console	Let INT10 (i.e. character output) calls print messages to debug output. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_INTERRUPTS	toplevel	bool	Log intXX calls	Print messages related to interrupt handling. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_CHECK_VMEM_ACCESS	toplevel	bool	Log special memory accesses	Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors) Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_MEM	toplevel	bool	Log all memory accesses	Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions. Note: This option will increase the size of the coreboot image. If unsure, say N.
X86EMU_DEBUG_IO	toplevel	bool	Log IO accesses	Print I/O accesses made by option ROM. Note: This option will increase the size of the coreboot image. If unsure, say N.
LLSHELL	toplevel	bool	Built-in low-level shell	If enabled, you will have a low level shell to examine your machine. Put llshell() in your (romstage) code to start the shell. See src/arch/x86/llshell/llshell.inc for details.
POWER_BUTTON_DEFAULT_ENABLE	toplevel	hex		Select when the board has a power button which can optionally be disabled by the user.
POWER_BUTTON_DEFAULT_DISABLE	toplevel	hex		Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts.
POWER_BUTTON_FORCE_ENABLE	toplevel	hex		Select when the board requires that the power button is always enabled.
POWER_BUTTON_FORCE_DISABLE	toplevel	hex		Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground.
POWER_BUTTON_IS_OPTIONAL	toplevel	bool		Internal option that controls ENABLE_POWER_BUTTON visibility.
BOARD_HAS_HARD_RESET	toplevel.deprecated_options	bool		This variable specifies whether a given board has a reset.c file containing a hard_reset() function.
BOARD_HAS_FADT	toplevel.deprecated_options	bool		This variable specifies whether a given board has a board-local FADT in fadt.c. Long-term, those should be moved to appropriate chipset components (eg. southbridge).
HAVE_BUS_CONFIG	toplevel.deprecated_options	bool		This variable specifies whether a given board has a get_bus_conf.c file containing information about bus routing.
DRIVERS_PS2_KEYBOARD	toplevel.deprecated_options	bool	PS/2 keyboard init	Enable this option to initialize PS/2 keyboards found connected to the PS/2 port. Some payloads (eg, filo) require this option. Other payloads (eg, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds. If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y.