Board:google/butterfly

This page describes using coreboot on the HP Pavilion Chromebook 14.

See Chromebooks for additional details.

Linux quirks

SMBios motherboard name

The chromeos_laptop kernel module is responsible for detecting and making the touchpad work. The module will refuse to load if the SMBios motherboard is not one of the known models. Hence, the SMBIOS_PRODUCT_NAME needs to contain "Butterfly" for chromeos_laptop to load.

Spurious resume

By default, linux will enable the touchpad buttons as a wakeup source. Since the lid is fairly flexible, gentle pressure will bend it enough to press one of the buttons, resulting in an unwanted resume. Placing the laptop in a backpack or holding it like a book is almost certain to cause a resume. This is a result as the touchpad being declared as a wakeup source in mainboard.asl.

$ cat /proc/acpi/wakeup
Device  S-state   Status   Sysfs node
TPAD      S3    *enabled   pnp:00:00

While, one solution is to hack mainboard.asl, it is also possible to disable the touchpad resume by the following command:

# echo TPAD > /proc/acpi/wakeup

EHCI debug port

With the default settings, the USB port next to the HDMI connector is the EHCI debug port.

Make a backup of the original ROM

With this chromebook, making a backup of the original ROM is highly recommended. Use the usual procedure of entering developer mode and backing up with the built-in flashrom before proceeding.

Building a complete coreboot image

General options

The following options will need to be enabled to get a working image:

General setup  --->  [*] Allow use of binary-only repository
Chipset  ---> [*] Add a System Agent binary
Chipset  ---> [*] Add Intel Management Engine firmware

The Video BIOS is available in the blobs repository:

VGA BIOS  ---> [*] Add a VGA BIOS image
VGA BIOS  ---> VGA BIOS path and filename: "3rdparty/mainboard/google/butterfly/snm_2130_coreboot.bin"

It's also a good idea to enable console via CBMEM, while disabling serial and EHCI debug:

Console  ---> [ ] Serial port console output
Console  ---> [ ] USB 2.0 EHCI debug dongle support
Console  ---> [*] Send console output to a CBMEM buffer
Console  ---> [*]   Show POST codes on the debug console

Unless you plan to run ChromeOS, disable ChromeOS features:

ChromeOS  ---> [ ] Build for ChromeOS 

The following options may(TM) make life easier in the future:

General setup  ---> [*] Use CMOS for configuration values
General setup  ---> [*] Create a table of timestamps collected during boot

Including the MAC address and keyboard layout

The coreboot that ships with the laptop will read the keyboard layout and MAC address from the flash. Since ChromeOS uses a different layout than CBFS, the region containing these parameters must me included in the CBFS of the custom coreboot. When not building for ChromeOS, coreboot will read this region from a CBFS file named vpd.bin. NOTE: This will only work when "Builf for ChromeOS" is NOT selected. If building for ChromeOS, coreboot will ignore vpd.bin, and try to locate these parameters using fmap.

Get 'flashmap'

$ git clone https://chromium.googlesource.com/chromiumos/third_party/flashmap

Find the RO_VPD section

Build flashmap, then run fmap_decode on the extracted chromebook firmware.

$ ./fmap_decode original_chrome_image.rom

Locate the RO_VPD section in the output:

area_offset="0x00600000" area_size="0x00004000" area_name="RO_VPD" area_flags_raw="0x01" area_flags="static"

Extract the RO_VPD section from ROM image.

First, convert area_offset and area_size to decimal, as dd does not accept hexadecimal input, then use dd to extract the RO_VPD section.

$ dd if=original_chrome_image.rom bs=1 skip=ibs=$((area_offset)) count=$((area_size)) of=vpd.bin

Insert vpd.bin in the custom coreboot image:

$ cbfstool build/coreboot.rom add -f vpd.bin -n vpd.bin -t raw