Board:lenovo/x60: Difference between revisions
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== Documentation == | == Documentation == | ||
* The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom] | * The touchscreen serial port is on irq 5 at port 0x0200. [http://forum.bongofish.co.uk/index.php?topic=2307.0 Some additional info from a x61t wacom] | ||
# OLD INFO | |||
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page: | |||
== Flashing on the laptop instructions. == | |||
'''Lenovo X60''', '''X60s''', '''T60''' and '''T60p''' flashing instructions. | |||
These Lenovo laptops have a register that must be flipped before coreboot can be flashed. | |||
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others. | |||
You will need: the [http://flashrom.org/Download#Installation_from_source flashrom source] (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and [http://git.stuge.se/?p=bucts.git the bucts utility]. | |||
# Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode. | |||
#* Find the definition of your flash chip in flashrom's flashchips.c | |||
#** Optionally, you can copy the existing definition as it is done in [http://patchwork.coreboot.org/patch/3621/ this patch]. This will allow to switch between the two definitions with the -c parameter. Be sure to change the <code>.name</code> field in that case (e.g. <code>.name = "SST25VF016B-RES",</code>). | |||
#* Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g. <code>.probe = probe_spi_res2,</code> if the chip replies with one byte vendor ID and one byte model ID) | |||
#* Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g. <code>.model_id = 0x14,</code>) | |||
#* Change the .write field to spi_chip_write_1 (i.e. <code>.write = spi_chip_write_1,</code>) | |||
# Run <code>flashrom -p internal -r factory.bin</code> | |||
#: This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates. | |||
# Run <code>dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k</code> | |||
# Run <code>dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump</code> | |||
#: Verify that the complete range is filled with ff bytes before proceeding! The above command must output: | |||
#: <code>0000000 ffff ffff ffff ffff ffff ffff ffff ffff</code> | |||
#: <code>*</code> | |||
#: <code>0010000</code> | |||
#: If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused. | |||
# Run <code>dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc</code> | |||
# Run <code>bucts 1</code> | |||
# Run <code>flashrom -p internal -w coreboot.rom</code> | |||
#: This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see [http://www.flashrom.org/pipermail/flashrom/2012-April/009124.html Peter's mail] before you panic. | |||
# Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot | |||
# Revert all changes made to flashrom (maybe backup the binary for later experiments) | |||
# Run <code>flashrom -p internal -w coreboot.rom</code>. | |||
#: This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS. | |||
# Run <code>bucts 0</code> | |||
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575 | |||
== Recovery == | |||
If you had a bad flash you will need a recovery method. | |||
If you only set bucts, then rebooted without doing any flash writes, things might be easier: | |||
bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted). | |||
After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal. | |||
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds. | |||
=== Required/advised hardware and informations === | |||
* [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf X60 Hardware Maintenance Manual] or [http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf T60 Hardware Maintenance Manual] for disassembling the laptop | |||
* An SO-8 IC clip, like the [http://www.tme.eu/en/details/pom-5250/test-clips/pomona/5250/ Pomona 5250] for instance. | |||
* An external flashrom programmer | |||
=== Howto === | |||
0. wire the pomona clip to a programmer that way: | |||
From the #coreboot IRC Channel on FreeNode servers: | |||
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins | |||
[...] | |||
Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6 | |||
[...] | |||
Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip | |||
[...] | |||
Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected | |||
[...] | |||
Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break | |||
[...] | |||
Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside | |||
Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside | |||
[...] | |||
Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens | |||
[...] | |||
Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer | |||
Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip | |||
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked... | |||
# Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard... | |||
# connect the pomona clip to the BIOS chip | |||
# flash coreboot or the BIOS | |||
# remount the laptop | |||
== Coreboot standard configuration == | |||
* It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN: | |||
[ ] Run VGA Option ROMs | |||
in make menuconfig. | |||
Note that you still need to include the option rom in coreboot: | |||
[*] Add a VGA BIOS image | |||
See [[VGA_support]] for details on how to include the VGA BIOS image. | |||
* Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN). | |||
From the #coreboot IRC Channel on FreeNode servers: | |||
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels | |||
[...] | |||
Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that | |||
Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;) | |||
== Last tested revision on the X60 == | |||
4bd7b0cbadabb45f9131da03121a6ca284f24f35 | |||
== Status == | |||
* [[Thinkpad_X60s|Thinkpad X60s Status]] |
Revision as of 20:03, 9 April 2015
Coreboot supports all variants of the ThinkPad X60 Series. (X60, X60s, X60 Tablet).
Aside from pre-sales configuration (display, processor speed, optional components) it looks like every X60 variant uses the same motherboard schematic.
Status
- Some ACPI issues with Windows needs to be fixed.
- Works well with GNU/Linux.
- The Wacom Digitizer now works on the X60 Tablet.
Installation and Flashing
Follow the tutorial below to install Coreboot on the ThinkPad X60 Series.
Board:lenovo/x60/Installation
Wifi chipsets
Lenovo BIOS has a whitelist of approved PCI ID's for wifi cards. Coreboot does not, so you are free to use any wifi chipset of your choosing once coreboot is installed.
The Libreboot distribution lists Wifi chipsets not needing proprietary software to work.
Status
Device/functionality | Status | Comments | ||||||
---|---|---|---|---|---|---|---|---|
CPU | ||||||||
CPU works | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Core Duo Mobile (L2300), PBGA479 | ||||||
L1 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L2 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
L3 cache enabled | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multiple CPU support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Multi-core support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Hardware virtualization | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
RAM | ||||||||
EDO | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SDRAM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SO-DIMM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DDR2 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
DDR3 | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Dual channel support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
ECC support | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Hardware | ||||||||
On-board IDE 3.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board IDE 2.5" | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board SATA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board SCSI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Ethernet | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Intel 82573L | ||||||
On-board Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
On-board Modem | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Untested | |||||||
On-board FireWire | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Smartcard reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board CompactFlash | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board PCMCIA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | Ricoh rl5c476 | ||||||
On-board Wifi | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board Bluetooth | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
On-board SD card reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Add-on slots/cards | ||||||||
ISA add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Audio/Modem-Riser (AMR/CNR) cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Mini-PCI add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Mini-PCI-Express add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
PCI-X add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
AGP graphics cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x1 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x2 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x4 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x8 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x16 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PCI Express x32 add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
HTX add-on cards | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Legacy / Super I/O | ||||||||
Floppy | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Serial port 1 (COM1) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | located in Ultrabase X6 | ||||||
Serial port 2 (COM2) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Parallel port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PS/2 keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
PS/2 mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Game port | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Infrared | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | WIP | Submited for review | ||||||
PC speaker | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
DiskOnChip | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Input | ||||||||
Trackpoint | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Touchpad | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fn Hotkeys | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Fingerprint Reader | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Laptop | ||||||||
Docking VGA | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking USB | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Audio | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Docking Displayport | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Thinklight | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Webcam | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Miscellaneous | ||||||||
Sensors / fan control | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Hardware watchdog | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
SMBus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
CAN bus | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
CPU frequency scaling | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Other powersaving features | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
ACPI | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Reboot | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Poweroff | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Suspend | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Nonstandard LEDs | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | LEDs are controlled by Embedded Controller (EC). Working without special support. | ||||||
High precision event timers (HPET) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | |||||||
Random number generator (RNG) | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A | |||||||
Wake on modem ring | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Wake on LAN | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Wake on keyboard | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Wake on mouse | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
TPM | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown | |||||||
Flashrom | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | See Lenovo_x60x |
Laptop specific | ||||||||
Tablet Touchscreen | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | x60 tablet wacom "penabled" | ||||||
thinkpad_acpi module compatibility | OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK | modprobe thinkpad_acpi works |
proprietary components status
- CPU Microcode (optional?) - works fine without. See http://download.intel.com/design/mobile/SPECUPDT/30922214.pdf
- VGA option rom (optional): Native graphics initialization (free replacement) is also available and merged in the master repo. Note that the replacement doesn't work yet with seabios but works with grub(as a payload) or libpayload based payloads. SeaBIOS can be used with SeaVGABIOS (coreboot linear framebuffer option in seabios menuconfig) but the native graphics implementation currently lacks INT 10H and VBT.
- EC(Embedded Controller) => you do not have to touch it(just leave it where it is)
Building the ROM without proprietary blobs
This basically means:
- No microcode updates
- Native graphics (replacement for the proprietary Video BIOS / VGA Option ROM)
- GRUB2 payload
In this configuration, only GNU/Linux is known to work. If you plan to use other operating systems, you might be out of luck.
Download coreboot like usual:
git clone http://review.coreboot.org/coreboot cd coreboot
At the time of writing for (for these instructions), the following git revision was used:
git reset --hard 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e
Install all of the coreboot build dependencies listed at Build_HOWTO and then build the crossgcc toolchain:
make crossgcc-i386
Apply the following patches in this order:
# Text mode patch for X60 native graphics (main patch already merged in coreboot. See 6723 on coreboot gerrit) git fetch http://review.coreboot.org/coreboot refs/changes/25/6725/3 && git cherry-pick FETCH_HEAD # Permanently enable wlan/wwan/bluetooth/trackpoint git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/3 && git cherry-pick FETCH_HEAD # If you want legacy brightness controls (if using this, make sure not to include the ACPI brightness patch below): git fetch http://review.coreboot.org/coreboot refs/changes/48/7048/4 && git cherry-pick FETCH_HEAD # OR if you want ACPI brightness controls (if using this, make sure not to include the legacy brightness patch above): git fetch http://review.coreboot.org/coreboot refs/changes/31/6731/7 && git cherry-pick FETCH_HEAD # Fix uneven backlight levels (for ACPI brightness controls): git fetch http://review.coreboot.org/coreboot refs/changes/49/7049/1 && git cherry-pick FETCH_HEAD # ACPI brightness patches above were abandoned due to Windows incompatibility. If you only want to use GNU/Linux, then it should work fine.
Now you will want this basic configuration for X60/X60s (in make menuconfig):
General setup / Expert mode = enable General setup / Local version string = 7BETC7WW (2.08 ) Mainboard / Mainboard vendor = Lenovo Mainboard / Mainboard model = ThinkPad X60 / X60s / X60t Mainboard / ROM chip size = 2048 KB (2 MB) Mainboard / SMBIOS Serial Number = L3BH242 Mainboard / SMBIOS Version Number = ThinkPad X60s Mainboard / SMBIOS Manufacturer = LENOVO Mainboard / SMBIOS Product name = 1702L8G Chipset / Include CPU microcode in CBFS = Do not include microcode updates Devices / Use native graphics initialization = enable Display / Keep VESA framebuffer = disable (disable for text-mode graphics, enable for coreboot vesa framebuffer) Generic Drivers / Digitizer = Autodetect Console / Send console output to a CBMEM buffer = enable Payload / Add a payload = An ELF executable payload Payload / Payload path and filename = grub.elf Now go back into Devices: Devices / Run VGA Option ROMs = disable Devices / Run Option ROMs on PCI devices = disable
Alternatively for X60 Tablet; it's the same as above, but with these differences:
General setup / Local version string = 7JET23WW (1.08 ) Mainboard / SMBIOS Serial Number = L3B8281 Mainboard / SMBIOS Version Number = ThinkPad X60 Tablet Mainboard / SMBIOS Product name = 6364WJ1 Generic Drivers / Digitizer = Present
SMBIOS values were taken by running dmidecode with the factory BIOS.
Note, the above assumes that you already built your grub.elf from source along with everything that you need. Building GRUB is not covered here.
Put your grub.elf in the coreboot directory and then run make. Alternatively, you could go back into menuconfig and select coreboot's own GRUB payload config, which will automatically download and build the GRUB payload. Building it yourself can be more flexible, though, since you get to choose what modules you want and you can use your own configs.
TODO
Non-free components replacements
Replace the non-free VGA option rom by making native graphics init work.(native graphics available in master)- Create a Native graphics<->VGA option rom. SeaVGABIOS (part of SeaBIOS) might be the answer. INT 10H and VBT are missing in native graphics.
Make backlight work without the non-free option rom.See [1]
Windows currently doesn't boot (STOP A5 error)
Windows 7 was tested and fails to boot at the moment.
The native graphics implementation lacks INT 10H and VBT, and GRUB cannot boot it. Booting with SeaBIOS+SeaVGABIOS results in graphical corruption (and no boot).
Booting with SeaBIOS and the VGA ROM (vbios) can be used to boot it, but booting ends with the message outlined here: STOP A5
More information can be found here
high pitched noise from the board during low power states
During low power state (cstate 3), a high-pitched "humming" noise eminates from the board. Some discussion has been made about this; suggestions include "using an oscilliscope in clever ways" (to detect where the noise is coming from to debug the issue). There are some workarounds:
Use "idle=halt" (higher power consumption) or "processor.max_cstate=2" (higher power consumption, but not as bad) kernel parameter in GRUB. These increase heat and power consumption.
Another option (for increased battery life and lower temperatures) is to use powertop --auto-tune, or set 'Tunables' in powertop (without any parameters).
Other things
- Add support for more batteries in ACPI.
- Make the wifi card and/or the laptop produce less heat.
- Sometimes some dock USB port aren't initialized => fix that
- Fix that warning:
[ 14.566817] ACPI Warning: 0x00000400-0x0000041f SystemIO conflicts with Region \_SB_.PCI0.SBUS.SMBI 1 (20130117/utaddress-251)
By using that advise:
<phcoder> GNUtoo-x60: in this case it looks like same range is declared twice in DSDT/SSDT
Documentation
- The touchscreen serial port is on irq 5 at port 0x0200. Some additional info from a x61t wacom
- OLD INFO
This page underwent massive changes, some of which weren't good. Below is a copy of what used to be on the old page:
Flashing on the laptop instructions.
Lenovo X60, X60s, T60 and T60p flashing instructions.
These Lenovo laptops have a register that must be flipped before coreboot can be flashed.
For those/some models with SPI flash chips you have also to modify flashrom. Because the chipset locks down the available commands that flashrom can send to the flash chip, you also need to change the flashrom source in a way that is not suitable to upstream. Flash chips can be identified by various commands (REMS*, RDID etc.). Some of them reply with an ID for the vendor and the exact chip model; others just reply with a single byte which is fine if there is only a small number of chips to distinguish, but won't work for the huge number of flash chips known to flashrom. The problem with the vendor BIOS is that it forbids the higher quality identification commands, so you need to force flashrom to use the lower quality opcode for the chip in your Thinkpad. You have to know the chip model beforehand (e.g. by inspection). Known models on the x60s are SST25VF016B, MX25L1605D and maybe others.
You will need: the flashrom source (at least r1613 to make sure the laptops are whitelisted to work with flashrom), a small modification of it (as explained below in detail), and the bucts utility.
- Patch flashrom to use RES SPI identification and spi_chip_write_1 for your flash chip, as well as change the flash chip model id to fit the RES opcode.
- Find the definition of your flash chip in flashrom's flashchips.c
- Optionally, you can copy the existing definition as it is done in this patch. This will allow to switch between the two definitions with the -c parameter. Be sure to change the
.name
field in that case (e.g..name = "SST25VF016B-RES",
).
- Optionally, you can copy the existing definition as it is done in this patch. This will allow to switch between the two definitions with the -c parameter. Be sure to change the
- Change the .probe field to probe_spi_resN where N equals the number of ID bytes the flash replies to the RES ID command (e.g.
.probe = probe_spi_res2,
if the chip replies with one byte vendor ID and one byte model ID) - Change the .model_id field to the RES model ID given in the datasheet of the flash chip (e.g.
.model_id = 0x14,
) - Change the .write field to spi_chip_write_1 (i.e.
.write = spi_chip_write_1,
)
- Find the definition of your flash chip in flashrom's flashchips.c
- Run
flashrom -p internal -r factory.bin
- This step is IMPORTANT since the factory BIOS in your machine is tied to your particular system board (or "planar" in IBM FRU terms) with a unique ID not present in factory BIOS updates.
- Run
dd if=coreboot.rom of=top64k.bin bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x10000] count=64k
- Run
dd if=coreboot.rom bs=1 skip=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k | hexdump
- Verify that the complete range is filled with ff bytes before proceeding! The above command must output:
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0010000
- If this is not the case, the coreboot image needs to be rebuilt with the second-to-last 64kbyte block unused.
- Run
dd if=top64k.bin of=coreboot.rom bs=1 seek=$[$(stat -c %s coreboot.rom) - 0x20000] count=64k conv=notrunc
- Run
bucts 1
- Run
flashrom -p internal -w coreboot.rom
- This will be slow, it will output errors for addresses 0x0 and 0x1f0000 when working with a 2 Mbyte flash chip, and it will say "FAILED!" at the end, see Peter's mail before you panic.
- Power cycle the machine (i.e. a cold boot, not just a reboot), now starting with coreboot
- Revert all changes made to flashrom (maybe backup the binary for later experiments)
- Run
flashrom -p internal -w coreboot.rom
.- This will successfully overwrite the entire flash chip, including the last 64k that were write protected with the factory BIOS.
- Run
bucts 0
See also http://thread.gmane.org/gmane.linux.bios/69354 http://thread.gmane.org/gmane.linux.bios.flashrom/575
Recovery
If you had a bad flash you will need a recovery method.
If you only set bucts, then rebooted without doing any flash writes, things might be easier: bucts sets a register that lives on the RTC well, ie. it is powered by the same source that keeps the clock alive. Usually that's a battery on the mainboard, and often there's some way to cut the source (by removing the battery, a jumper, or pads that can be shorted). After doing that (for a few seconds, there might be some capacitors in the way that keep power stable), the register should be reset and the system should boot as normal.
On the x60x, bucts issues might also be solved by "discarging RTC", which is done by pressing the power button 5 times for 10 seconds.
Required/advised hardware and informations
- X60 Hardware Maintenance Manual or T60 Hardware Maintenance Manual for disassembling the laptop
- An SO-8 IC clip, like the Pomona 5250 for instance.
- An external flashrom programmer
Howto
0. wire the pomona clip to a programmer that way:
From the #coreboot IRC Channel on FreeNode servers:
Oct 01 15:35:48 <CareBear\> one important thing is that when you connect the clip to the X60 you should not connect all pins [...] Oct 01 15:36:22 <CareBear\> only connect these pins: 1, 2, 4, 5, 6 [...] Oct 01 15:37:21 <CareBear\> also important: first connect charger to laptop, then connect the clip [...] Oct 01 17:49:41 <CareBear\> GNUtoo-desktop : the mainboard must be powered off, but with the charger connected [...] Oct 01 17:50:39 <CareBear\> um, that way there is no way anything will break [...] Oct 01 17:51:00 <CareBear\> it is important not to connect 3v3 from the outside Oct 01 17:51:39 <CareBear\> because the correct power sequencing is not known, and if any other rail must come on before the standby 3v3 then the machine may well break when 3v3 is applied from the outside [...] Oct 01 17:52:48 <CareBear\> it may also be fine - but it is unknown what happens [...] Oct 01 17:53:47 <CareBear\> not supplying 3v3 from the outside is safer Oct 01 17:54:25 <CareBear\> and because the machine is powered off, there is no risk of the chipset accessing the flash chip
In another hand I didn't follow that and wired it without powering the mainboard(mainboard disconnected from power plug, no battery in) and with all pins and it worked...
- Disassemble carefully the laptop, the SO-8 chip is on the bottom of the mainboard...
- connect the pomona clip to the BIOS chip
- flash coreboot or the BIOS
- remount the laptop
Coreboot standard configuration
- It's advised to make SeaBios(instead of coreboot) run the VGA option rom by disabling CONFIG_VGA_ROM_RUN:
[ ] Run VGA Option ROMs
in make menuconfig. Note that you still need to include the option rom in coreboot:
[*] Add a VGA BIOS image
See VGA_support for details on how to include the VGA BIOS image.
- Also disable CONFIG_S3_VGA_ROM_RUN which is for really old linux kernels(2.4) (which is disabled automatically if you don't select CONFIG_VGA_ROM_RUN).
From the #coreboot IRC Channel on FreeNode servers:
Oct 04 13:47:09 <patrickg> that's about running vga init on s3 wakeup - required for some older linux kernels [...] Oct 04 13:47:25 <patrickg> BIOSes call it "POST on wakeup" or sth like that Oct 04 13:47:30 <patrickg> older ~ 2.4 class ;)
Last tested revision on the X60
4bd7b0cbadabb45f9131da03121a6ca284f24f35