Build HOWTO: Difference between revisions

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* gcc / g++
* gcc / g++
* make
* make
* cmake
* ncurses-dev (for '''make menuconfig''')
* ncurses-dev (for '''make menuconfig''')



Revision as of 22:54, 15 June 2015

make menuconfig in coreboot

This page describes how you can build a coreboot image for your specific mainboard.

Requirements

  • gcc / g++
  • make
  • cmake
  • ncurses-dev (for make menuconfig)

Optional:

  • doxygen (for generating/viewing documentation)
  • iasl (for targets with ACPI support)
  • gdb (for better debugging facilities on some targets)
  • flex and bison (for regenerating parsers)

Building a payload

First you need to download the source code for the payload of your choice and build it.

Instructions for building the various payloads are not covered on this page, please see Payloads and the wiki page for the respective payload for details.

The result of this step should be an ELF file (e.g. filo.elf, or coreinfo.elf) which you can use with coreboot (see below).

Building coreboot

First, get the latest coreboot version from our git repository:

$ git clone http://review.coreboot.org/p/coreboot
$ cd coreboot
$ git submodule update --init --checkout

The last step is important! It checks out a sub-repository in the 3rdparty directory.

In the coreboot directory you can configure the build-time options of coreboot:

$ make menuconfig

In that menu (which may look familiar, as other projects such as the Linux kernel or busybox use the same system), select at least the following options:

  • Enter the Mainboard menu.
    • In Mainboard vendor select the vendor of your board.
    • In Mainboard model select your exact mainboard name.
    • In ROM chip size select the exact size of the flash ROM chip you want to flash the coreboot image on. (see output of flashrom command)
  • Enter the Payload menu.
    • By default, the SeaBIOS payload will be downloaded and built during the coreboot build process. If you want to use another payload:
      • Set the Add a payload option to An ELF executable payload.
      • Then, specify the file name and path to your payload file (which you built before).

You also need to build crossgcc (highly recommended because distributions patch gcc in ways that introduce bugs when building coreboot):

$ make crossgcc

In case something fails, try to search for the relevant log (find . -name '*.log' | xargs grep Error) and examine last few lines of it.

That's the bare minimum. Feel free to adjust the other settings to your needs (see Coreboot Options for the full list), then exit menuconfig and build the coreboot image:

$ make

The file build/coreboot.rom is your final coreboot image you can flash onto a ROM chip or add payloads to with cbfstool.

Compiling with Clang/LLVM

We have been working on building coreboot with clang/llvm and it basically works. Remaining issues can be reported upstream and then block this meta bug here:

META Compiling the Coreboot with clang

The default and recommended flow is still to use crossgcc.

Known issues

Make sure you really have all the requirements installed!

With certain versions of the gcc/ld toolchain shipped in some Linux distributions, it's possible that you'll see the following error when building coreboot:

src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards

This is a known bug in those versions of the toolchain. Before sending a complaint message to our mailing list, please try to switch to our reference cross-compilation toolkit then recompile the sources. To switch to the cross-compiler just run

$ make crossgcc

Then remove the .xcompile file and retry the compilation process:

$ rm .xcompile
$ make

Development version

If you want to contribute a patch or report an issue about coreboot, you will need to set up your environment for full development.

You must run make crossgcc and rebuild coreboot before reporting an issue or contributing a patch.

To get set up to submit a patch please run make gitconfig, then register with gerrit.

Flashing coreboot

You can flash the coreboot image on a flash ROM chip using either an external EEPROM-programmer or a mainboard using the flashrom user-space utility.