Board:lowrisc/nexys4ddr: Difference between revisions
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''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."'' | ''"[https://www.lowrisc.org lowRISC] is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."'' | ||
This coreboot port runs on the lowRISC bitstream for the Nexys 4 DDR FPGA development board. | This coreboot port runs on the lowRISC bitstream for the [https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ Nexys 4 DDR] FPGA development board. | ||
== Booting coreboot == | == Booting coreboot == | ||
Revision as of 18:35, 22 December 2016
"lowRISC is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year [2016]."
This coreboot port runs on the lowRISC bitstream for the Nexys 4 DDR FPGA development board.
Booting coreboot
- make crossgcc-riscv
- select the board in menuconfig
- convert the board to an ELF file through util/riscvtools/make-spike-elf.sh
- Copy coreboot.elf on a µSD card as boot.bin
- Boot the FPGA board with this µSD card