Glossary: Difference between revisions

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(Wikified the glossary (part 1).)
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== '''Glossary''' ==  
== A ==


'''ACPI''' (Advanced Configuration & Power Interface) is an industry standard
=== ACPI ===
for letting the OS control power management.
The '''Advanced Configuration & Power Interface''' is an industry standard for letting the OS control power management.
* http://www.acpi.info/
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface


http://www.acpi.info/
=== AGP ===
'''Advanced Graphics Port'''
* http://en.wikipedia.org/wiki/AGP


http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
=== AGP Aperture ===
----------------------------------------------------
The memory range that is set aside for AGP access.
'''AGP''' (Advanced Graphics Port).
* http://en.wikipedia.org/wiki/AGP
 
=== AHCI ===
The '''Advanced Host Controller Interface'''. Describes the register-level interface for a SATA host controller.
* http://encyclopedia.thefreedictionary.com/ahci
* http://www.intel.com/technology/serialata/ahci.htm
 
=== APIC ===
'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
* http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
* http://osdev.berlios.de/pic.html
 
 
== B ==
 
=== BAR ===
Base Address Register.
 
 
== C ==
 
=== CAR ===
Cache as RAM.


http://en.wikipedia.org/wiki/AGP
----------------------------------------------------
'''AGP Aperture'''. The memory range that is set aside for AGP access.


http://en.wikipedia.org/wiki/AGP
== D ==
----------------------------------------------------
'''AHCI''' (Advanced Host Controller Interface). Describes the register-level
interface for a SATA host controller.


http://encyclopedia.thefreedictionary.com/ahci
=== DCR ===
Decode Control Register.


http://www.intel.com/technology/serialata/ahci.htm
=== DID ===
----------------------------------------------------
Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.
'''APIC''' (Advanced Programmable Interrupt Controller). An advanced version of
a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.


http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
=== DMA ===
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
* http://encyclopedia.thefreedictionary.com/direct%20memory%20access


http://osdev.berlios.de/pic.html
----------------------------------------------------
'''BAR''' (Base Address Register)
----------------------------------------------------
'''CAR''' (Cache as RAM)
----------------------------------------------------
'''DCR''' (Decode Control Register)
----------------------------------------------------
'''DID''' - Device ID, a way of identifying the hardware in question. See VID for more info.
----------------------------------------------------
'''DMA''' (Direct Memory Access) allows certain hardware subsystems within a
computer to access system memory for reading and/or writing independently
of the main CPU. Examples of systems that use DMA: Hard Disk Controller,
Disk Drive Controller, Graphics Card, Sound Card.


DMA is an essential feature of all modern computers, as it allows devices
== F ==
of different speeds to communicate without subjecting the CPU to a massive
interrupt load.


http://encyclopedia.thefreedictionary.com/direct%20memory%20access
=== Framebuffer ===
----------------------------------------------------
The '''Framebuffer''' is a part of RAM in a computer allocated to hold the
graphics information for one frame or picture. This information typically
consists of color values for every pixel on the screen.


The '''Framebuffer''' is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.
A framebuffer is either:
A framebuffer is either:
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
* Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
* On-screen, meaning that the framebuffer is directly coupled to the visible display
* On-screen, meaning that the framebuffer is directly coupled to the visible display


http://encyclopedia.thefreedictionary.com/framebuffer
* http://encyclopedia.thefreedictionary.com/framebuffer
----------------------------------------------------
 
'''GART''' (Graphics Address Relocation Table)
 
== G ==
 
=== GART ===
Graphics Address Relocation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752
 
=== GATT ===
Graphics Aperture Translation Table.
* http://www.linuxelectrons.com/article.php/20031021142247752
 
=== GPIO ===
General Purpose Input/Output.
* http://en.wikipedia.org/wiki/GPIO


http://www.linuxelectrons.com/article.php/20031021142247752
----------------------------------------------------
'''GATT''' (Graphics Aperture Translation Table)


http://www.linuxelectrons.com/article.php/20031021142247752
== H ==
----------------------------------------------------
'''GPIO''' (General Purpose Input/Output).


http://en.wikipedia.org/wiki/GPIO
=== Hypertransport ===
----------------------------------------------------
'''Hypertransport'''


A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.


http://computing-dictionary.thefreedictionary.com/hypertransport
* http://computing-dictionary.thefreedictionary.com/hypertransport
* http://www.hypertransport.org
 
 
== I ==


http://www.hypertransport.org
=== I2C ===
----------------------------------------------------
 
'''I2C''' - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient
'''Inter-Integrated-Circuit''', a bidirectional 2-wire bus for efficient inter-IC control.
inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for
* http://www.esacademy.com/faq/i2c/index.htm
more info.


Code examples(?): ...
=== IDSEL/AD ===
------------------------------------------
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
'''IDSEL/AD''' (Initialization Device SELect/Address and Data).
* http://www.techfest.com/hardware/bus/pci.htm
* http://www.fpga4fun.com/PCI4.html


Each PCI slot has a signal called IDSEL. It is used to differentiate
between the different cards?


http://www.techfest.com/hardware/bus/pci.htm
== L ==


http://www.fpga4fun.com/PCI4.html
=== LPC ===
----------------------------------------------------
'''Low Pin Count''', an interface aimed at replacing the ISA bus.
'''LPC''' (Low Pin Count). An interface aimed at replacing he ISA bus.
* http://www.intel.com/design/chipsets/industry/lpc.htm


http://www.intel.com/design/chipsets/industry/lpc.htm
=== LRU ===
----------------------------------------------------
'''Least Recently Used''', a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
'''LRU''' (Least Recently Used). A rule used in operating systems that utilises
* http://computer.laborlawtalk.com/Least%20Recently%20Used
a paging system. LRU selects a page to be paged out if it has been
used less recently than any other page. This may be applied to a cache
system as well.


http://computer.laborlawtalk.com/Least%20Recently%20Used
----------------------------------------------------
'''MII''' (Media Independent Interface). This is a chip commonly found
on ethernet devices, together with a PHY.


http://en.wikipedia.org/wiki/MII
== M ==
----------------------------------------------------
'''MMIO''' (Memory-mapped I/O) and port I/O (also called port-mapped I/O or
PMIO) are two complementary methods of performing input/output
between the CPU and I/O devices in a computer.


http://encyclopedia.thefreedictionary.com/mmio
=== MII ===
----------------------------------------------------
'''Media Independent Interface'''. This is a chip commonly found on ethernet devices, together with a PHY.
'''MPTable''' (Multi Processor Table). Intel MP specification is a hardware
* http://en.wikipedia.org/wiki/MII
compatibility guide for machine hardware designers and OS software
writers to produce SMP-capable machines and OSes in a vendor-independent manner.
v1.1 and v1.4 versions exist.


http://www.uruk.org/~erich/mps.html
=== MMIO ===
'''Memory-mapped I/O''' and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
* http://encyclopedia.thefreedictionary.com/mmio


http://www.intel.com/design/pentium/datashts/242016.htm
=== MPTable ===
----------------------------------------------------
'''Multi Processor Table'''. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
'''MTRR''' (Memory Type Range Register). This can be used to control the way a
* http://www.uruk.org/~erich/mps.html
processor accesses memory ranges.
* http://www.intel.com/design/pentium/datashts/242016.htm


http://en.wikipedia.org/wiki/MTRR
=== MTRR ===
----------------------------------------------------
'''Memory Type Range Register'''. This can be used to control the way a processor accesses memory ranges.
'''OHCI''' (Open Host Controller Interface). IEEE1394 (Firewire) and
* http://en.wikipedia.org/wiki/MTRR
USB standard (mostly used by other companies than Intel)


http://encyclopedia.thefreedictionary.com/ohci


http://developer.intel.com/technology/1394/download/ohci_11.htm
== O ==
----------------------------------------------------
'''PAM''' (Programmable Attribute Map).


hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
=== OHCI ===
----------------------------------------------------
'''Open Host Controller Interface'''. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
'''PAT''' (Page Attribute Table). Can be used independently or in combination
* http://encyclopedia.thefreedictionary.com/ohci
with MTRR to setup memory type access ranges. Allows more finely-grained control
* http://developer.intel.com/technology/1394/download/ohci_11.htm
than MTRR.


http://www.intel.com/design/pentium4/manuals/index_new.htm


http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
== P ==
----------------------------------------------------
'''PAT''' (Performance Acceleration Technology).


http://www.intel.com/design/chipsets/pat.htm
=== PAM ===
----------------------------------------------------
'''Programmable Attribute Map'''. Hardware registers that describe how certain memory areas are accessed. The '''BIOS''' areas have a flash chip mapped on top of a piece of memory. By changing the '''PAM''' registers, accesses to these memory areas can be mapped to either the RAM or the flash device. '''Shadowing''' is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the '''PAM''' registers are part of the southbridge of a system.
'''PCI''' (Peripheral Component Interconnect).


http://encyclopedia.thefreedictionary.com/PCI
=== PAT ===
----------------------------------------------------
'''Page Attribute Table'''. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
'''PCI Configuration Space'''.
* http://www.intel.com/design/pentium4/manuals/index_new.htm
* http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10


http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space
=== PAT ===
Performance Acceleration Technology.
* http://www.intel.com/design/chipsets/pat.htm


http://www.techfest.com/hardware/bus/pci.htm
=== PCI ===
----------------------------------------------------
Peripheral Component Interconnect.
'''PCI Express''' or '''PCIe'''
* http://encyclopedia.thefreedictionary.com/PCI


http://computing-dictionary.thefreedictionary.com/PCI+Express
=== PCI Configuration Space ===
----------------------------------------------------
* http://encyclopedia.thefreedictionary.com/PCI%20Configuration%20Space
'''PHY''' (PHY layer device). A device that provides low level access
* http://www.techfest.com/hardware/bus/pci.htm
to the physical layer.


http://en.wikipedia.org/wiki/PHY
=== PCI Express / PCIe ===
* http://computing-dictionary.thefreedictionary.com/PCI+Express


http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer
=== PHY ===
----------------------------------------------------
'''PHY layer device'''. A device that provides low level access to the physical layer.
'''PIC''' (Programmable Interrupt Controller) is a device to control peripheral devices,
* http://en.wikipedia.org/wiki/PHY
offloading the main CPU.
* http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?physical+layer


http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
=== PIC ===
A '''Programmable Interrupt Controller''' is a device to control peripheral devices, offloading the main CPU.
* http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
* http://www.interq.or.jp/japan/se-inoue/e_pic1.htm


http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
=== PIO ===
----------------------------------------------------
'''Programmed Input/Output''' interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
'''PIO''' (Programmed Input/Output) interface is the original method used to
* http://encyclopedia.thefreedictionary.com/pio
transfer data between the CPU (through the IDE controller) and an IDE/ATA
device.


http://encyclopedia.thefreedictionary.com/pio
=== PIR ===
----------------------------------------------------
Programmable Interrupt Routing?
'''PIR''' (Programmable Interrupt Routing?)
----------------------------------------------------
'''PIRQ''' (Pci IRQ routing table).


http://www.microsoft.com/whdc/archive/pciirq.mspx
=== PIRQ ===
PCI IRQ routing table,
* http://www.microsoft.com/whdc/archive/pciirq.mspx
* http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148
* http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
* Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view


http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148
=== PLCC ===
'''Plastic Leaded Chip Carrier''', a square surface-mount chip package.
* http://www.webopedia.com/TERM/P/PLCC.html


http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
=== PLL ===
'''Phase Locked Loop''' is a device to keep (electrical) signals synchronised throughout the system.
* http://en.wikipedia.org/wiki/PLL


Interesting tool?:
=== POST ===
https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
The '''Power On Self Test''' is a test to check that devices the computer will rely on are functioning, and initializes devices.
----------------------------------------------------
* http://encyclopedia.thefreedictionary.com/booting
'''PLCC''' (Plastic Leaded Chip Carrier). A square Surface-mount chip package.


http://www.webopedia.com/TERM/P/PLCC.html
----------------------------------------------------
'''PLL''' (Phase Locked Loop) is a device to keep (electrical) signals synchronised
throughout the system.


http://en.wikipedia.org/wiki/PLL
== R ==
----------------------------------------------------
'''POST''' (Power On Self Test) is a test to check that devices the computer
will rely on are functioning, and initializes devices.


http://encyclopedia.thefreedictionary.com/booting
------------------------------------------
'''RDMA''' (Remote Direct Memory Access) is a concept whereby two or more
'''RDMA''' (Remote Direct Memory Access) is a concept whereby two or more
computers communicate via DMA directly from main memory of one system to
computers communicate via DMA directly from main memory of one system to
Line 221: Line 210:
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access
----------------------------------------------------
----------------------------------------------------
== S ==
'''SB''' (Southbridge)
'''SB''' (Southbridge)


Line 267: Line 259:
http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html
----------------------------------------------------
----------------------------------------------------
== T ==
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
'''TLB''' (Translation Lookaside Buffer). The TLB stores the most recently used
page-directory and page-table entries, which translates into speedier
page-directory and page-table entries, which translates into speedier
Line 274: Line 269:
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
----------------------------------------------------
----------------------------------------------------
== U ==
'''UC''' (strong UnCacheable). Memory type setting in MTRR/PAT.
'''UC''' (strong UnCacheable). Memory type setting in MTRR/PAT.


Line 297: Line 295:
http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm
----------------------------------------------------
----------------------------------------------------
== V ==
'''VID''' - Vendor ID, a way of identifying the hardware manufacturer. See
'''VID''' - Vendor ID, a way of identifying the hardware manufacturer. See
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and
'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and
Line 311: Line 312:
http://encyclopedia.thefreedictionary.com/VMEbus
http://encyclopedia.thefreedictionary.com/VMEbus
----------------------------------------------------
----------------------------------------------------
== W ==
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.
'''WB''' (Write-Back). Memory type setting in MTRR/PAT.


Revision as of 22:17, 6 October 2006

A

ACPI

The Advanced Configuration & Power Interface is an industry standard for letting the OS control power management.

AGP

Advanced Graphics Port

AGP Aperture

The memory range that is set aside for AGP access.

AHCI

The Advanced Host Controller Interface. Describes the register-level interface for a SATA host controller.

APIC

Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.


B

BAR

Base Address Register.


C

CAR

Cache as RAM.


D

DCR

Decode Control Register.

DID

Device ID, a way of identifying the hardware in question. See VID for more info.

DMA

Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.


F

Framebuffer

The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:

  • Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
  • On-screen, meaning that the framebuffer is directly coupled to the visible display


G

GART

Graphics Address Relocation Table.

GATT

Graphics Aperture Translation Table.

GPIO

General Purpose Input/Output.


H

Hypertransport

A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.


I

I2C

Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control.

IDSEL/AD

Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?


L

LPC

Low Pin Count, an interface aimed at replacing the ISA bus.

LRU

Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.


M

MII

Media Independent Interface. This is a chip commonly found on ethernet devices, together with a PHY.

MMIO

Memory-mapped I/O and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.

MPTable

Multi Processor Table. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.

MTRR

Memory Type Range Register. This can be used to control the way a processor accesses memory ranges.


O

OHCI

Open Host Controller Interface. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).


P

PAM

Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.

PAT

Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

PAT

Performance Acceleration Technology.

PCI

Peripheral Component Interconnect.

PCI Configuration Space

PCI Express / PCIe

PHY

PHY layer device. A device that provides low level access to the physical layer.

PIC

A Programmable Interrupt Controller is a device to control peripheral devices, offloading the main CPU.

PIO

Programmed Input/Output interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.

PIR

Programmable Interrupt Routing?

PIRQ

PCI IRQ routing table,

PLCC

Plastic Leaded Chip Carrier, a square surface-mount chip package.

PLL

Phase Locked Loop is a device to keep (electrical) signals synchronised throughout the system.

POST

The Power On Self Test is a test to check that devices the computer will rely on are functioning, and initializes devices.


R

RDMA (Remote Direct Memory Access) is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.

http://encyclopedia.thefreedictionary.com/Remote%20Direct%20Memory%20Access

S

SB (Southbridge)

Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...

SBA (SideBand Addressing)

http://www.linuxelectrons.com/article.php/20031021142247752

SIO (Serial Input/Output)

http://www.acronymfinder.com/af-query.asp?String=off&Acronym=sio&Find=Find&sourceid=mozilla-search

SMBus (System Management Bus) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.

http://www.smbus.org/

http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus See I2C for more info.

SMM (System Management Mode)

Processor mode that is mainly used for power management purposes.

SMRAM (System Management Random Access Memory).

SPD (Serial Presence Detect). On every (?) memory module there's an eprom that provides BIOS with information on how to properly configure the memory module.

http://www.simmtester.com/page/news/showpubnews.asp?num=101

SPI (Serial Peripheral Interface Bus) is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.

http://encyclopedia.thefreedictionary.com/Serial%20Peripheral%20Interface

http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

SuperIO is the chip that provides floppy, serial and parallel functionality/ports.

http://www.simtec.co.uk/products/EB7500ATX/files/EB7500ATX-mmap.html

T

TLB (Translation Lookaside Buffer). The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.

http://www.linuxelectrons.com/article.php/20031021142247752 For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1

U

UC (strong UnCacheable). Memory type setting in MTRR/PAT.

UC- (UnCacheable). Memory type setting in MTRR/PAT.

For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

UHCI (Universal Host Controller Interface). USB standard.

http://encyclopedia.thefreedictionary.com/dict.asp?Word=uhci

http://developer.intel.com/technology/usb/uhci11d.htm

The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students fpga project)

http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm

V

VID - Vendor ID, a way of identifying the hardware manufacturer. See 'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and 'http://pciids.sourceforge.net/' for more info.

A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.

VMEBus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus originally developed for the Motorola 68000.

http://encyclopedia.thefreedictionary.com/VMEbus

W

WB (Write-Back). Memory type setting in MTRR/PAT.

WC (Write-Combining). Memory type setting in MTRR/PAT.

WP (Write Protected). Memory type setting in MTRR/PAT.

WT (Write-Through). Memory type setting in MTRR/PAT.


For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3

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