Coreboot Options: Difference between revisions

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This is an automatically generated list of '''LinuxBIOS compile-time options'''.
This is an automatically generated list of '''coreboot compile-time options'''.


Last update: 2006/10/18 17:45:44.
Last update: 2008/01/27 01:59:29.


{| border="0"
{| border="0"
Line 89: Line 89:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_VERSION
COREBOOT_VERSION
|
|
"LinuxBIOS version"
"coreboot version"
|
|
"2.0.0"
"2.0.0"
Line 100: Line 100:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_EXTRA_VERSION
COREBOOT_EXTRA_VERSION
|
|


Line 111: Line 111:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_BUILD
COREBOOT_BUILD
|
|
"Build date"
"Build date"
Line 122: Line 122:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_COMPILE_TIME
COREBOOT_COMPILE_TIME
|
|
"Build time"
"Build time"
Line 133: Line 133:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_COMPILE_BY
COREBOOT_COMPILE_BY
|
|
"Who build this image"
"Who build this image"
Line 144: Line 144:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_COMPILE_HOST
COREBOOT_COMPILE_HOST
|
|
"Build host"
"Build host"
Line 155: Line 155:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_COMPILE_DOMAIN
COREBOOT_COMPILE_DOMAIN
|
|
"Build domain name"
"Build domain name"
Line 166: Line 166:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_COMPILER
COREBOOT_COMPILER
|
|
"Build compiler"
"Build compiler"
Line 177: Line 177:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_LINKER
COREBOOT_LINKER
|
|
"Build linker"
"Build linker"
Line 188: Line 188:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
LINUXBIOS_ASSEMBLER
COREBOOT_ASSEMBLER
|
|
"Build assembler"
"Build assembler"
Line 344: Line 344:
_ROMBASE
_ROMBASE
|
|
"Base address of LinuxBIOS in ROM"
"Base address of coreboot in ROM"
|
|
{PAYLOAD_SIZE}
{PAYLOAD_SIZE}
Line 355: Line 355:
_ROMSTART
_ROMSTART
|
|
"Start address of LinuxBIOS in ROM"
"Start address of coreboot in ROM"
|
|
none
none
Line 410: Line 410:
_RAMBASE
_RAMBASE
|
|
"Base address of LinuxBIOS in RAM"
"Base address of coreboot in RAM"
|
|
none
none
Line 421: Line 421:
_RAMSTART
_RAMSTART
|
|
"Start address of LinuxBIOS in RAM"
"Start address of coreboot in RAM"
|
|
none
none
Line 433: Line 433:
|
|
"Use data cache as temporary RAM if possible"
"Use data cache as temporary RAM if possible"
|
0
|
always
|
|- bgcolor="#eeeeee"
|
CAR_FAM10
|
"AMD family 10 CAR requires additional setup"
|
|
0
0
Line 509: Line 520:
XIP_ROM_BASE
XIP_ROM_BASE
|
|
"Start address of area to cache during LinuxBIOS execution directly from ROM"
"Start address of area to cache during coreboot execution directly from ROM"
|
|
0
0
Line 520: Line 531:
XIP_ROM_SIZE
XIP_ROM_SIZE
|
|
"Size of area to cache during LinuxBIOS execution directly from ROM"
"Size of area to cache during coreboot execution directly from ROM"
|
|
0
0
Line 586: Line 597:
LB_CKS_RANGE_START
LB_CKS_RANGE_START
|
|
"First CMOS byte to use for LinuxBIOS options"
"First CMOS byte to use for coreboot options"
|
|
49
49
Line 597: Line 608:
LB_CKS_RANGE_END
LB_CKS_RANGE_END
|
|
"Last CMOS byte to use for LinuxBIOS options"
"Last CMOS byte to use for coreboot options"
|
|
125
125
Line 641: Line 652:
CONFIG_CONSOLE_VGA
CONFIG_CONSOLE_VGA
|
|
"Log messages to VGA"
"Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
|
|
0
0
Line 708: Line 719:
|
|
"Log messages to 8250 uart based serial console"
"Log messages to 8250 uart based serial console"
|
0
|
always
|
|- bgcolor="#eeeeee"
|
CONFIG_USBDEBUG_DIRECT
|
"Log messages to ehci debug port console"
|
|
0
0
Line 1,002: Line 1,024:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_IDE_STREAM
CONFIG_IDE_PAYLOAD
|
|
"Boot from IDE device"
"Boot from IDE device"
Line 1,013: Line 1,035:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_ROM_STREAM
CONFIG_ROM_PAYLOAD
|
|
"Boot image is located in ROM"  
"Boot image is located in ROM"  
Line 1,024: Line 1,046:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_ROM_STREAM_START
CONFIG_ROM_PAYLOAD_START
|
|
"ROM stream start location"
"ROM stream start location"
Line 1,035: Line 1,057:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_COMPRESSED_ROM_STREAM
CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
"compressed boot image is located in ROM and is assumed to be NRV2B (deprecated)"
|
0
|
always
|
 
|- bgcolor="#eeeeee"
|
CONFIG_COMPRESSED_ROM_STREAM_NRV2B
|
|
"NRV2B compressed boot image is located in ROM"  
"NRV2B compressed boot image is located in ROM"  
Line 1,057: Line 1,068:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_COMPRESSED_ROM_STREAM_LZMA
CONFIG_COMPRESSED_PAYLOAD_LZMA
|
|
"LZMA compressed boot image is located in ROM"  
"LZMA compressed boot image is located in ROM"  
Line 1,068: Line 1,079:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_PRECOMPRESSED_ROM_STREAM
CONFIG_PRECOMPRESSED_PAYLOAD
|
|
"boot image is already compressed"  
"boot image is already compressed"  
Line 1,079: Line 1,090:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_SERIAL_STREAM
CONFIG_SERIAL_PAYLOAD
|
|
"Download boot image from serial port"
"Download boot image from serial port"
Line 1,090: Line 1,101:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_FS_STREAM
CONFIG_FS_PAYLOAD
|
|
"Boot from a filesystem"
"Boot from a filesystem"
Line 1,629: Line 1,640:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
HW_MEM_HOLE_SIZEK
MMCONF_SUPPORT_DEFAULT
|
"enable mmconfig for pci conf"
|
0
|
always
|
 
|- bgcolor="#eeeeee"
|
HW_MEM_HOLE_SIZEK
|
|


Line 1,647: Line 1,669:
|
|


|
|- bgcolor="#eeeeee"
|
CONFIG_VAR_MTRR_HOLE
|
"using hole in MTRR instead of increasing method"
|
1
|
always
|
|


Line 1,695: Line 1,728:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
DIMM_SUPPORT
HT3_SUPPORT
|
"Hypertransport 3 support, include ac HT and unganged sublink feature"
|
|
 
0
|
|
 
always
|
|


|
"0x%x"
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CPU_SOCKET_TYPE
EXT_RT_TBL_SUPPORT
|
|
"cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
"support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
|
|
0x10
0
|
|
always
always
Line 1,717: Line 1,750:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CPU_ADDR_BITS
EXT_CONF_SUPPORT
|
|
"CPU hardware address lines num, for AMD K8 could be 40, and GH could be 48"
"support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
|
|
36
0
|
|
always
always
Line 1,728: Line 1,761:
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_PCI_ROM_RUN
DIMM_SUPPORT
|
|
"Init PCI device option rom"
 
|
|
0
 
|
|
always
 
|
|
 
"0x%x"
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_PCI_64BIT_PREF_MEM
CPU_SOCKET_TYPE
|
|
 
"cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
|
|
 
0x10
|
|
 
always
|
|


|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
|
|
CONFIG_VIDEO_MB
CPU_ADDR_BITS
|
|
 
"CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
|
36
|
always
|
 
|- bgcolor="#eeeeee"
|
CONFIG_VGA_ROM_RUN
|
"Init x86 ROMs on VGA-class PCI devices"
|
0
|
always
|
 
|- bgcolor="#eeeeee"
|
CONFIG_PCI_ROM_RUN
|
"Init x86 ROMs on all PCI devices"
|
0
|
always
|
|


|- bgcolor="#eeeeee"
|
CONFIG_PCI_64BIT_PREF_MEM
|
|


|
|
|
|- bgcolor="#eeeeee"
|
CONFIG_AMDMCT
|
"use AMD MCT to init RAM instead of native code"
|
0
|
always
|
|- bgcolor="#eeeeee"
|
CONFIG_VIDEO_MB
|
|
|
|
|- bgcolor="#eeeeee"
|
CONFIG_SPLASH_GRAPHIC
|
"Paint a splash screen"
|
0
|
used
|
|- bgcolor="#eeeeee"
|
CONFIG_GX1_VIDEO
|
"Build in GX1's graphic support"
|
0
|
used
|
|- bgcolor="#eeeeee"
|
CONFIG_GX1_VIDEOMODE
|
"Define video mode after reset"
|
none
|
used
|
|


Revision as of 01:04, 27 January 2008

This is an automatically generated list of coreboot compile-time options.

Last update: 2008/01/27 01:59:29.

Option Comment Default Export Format

ARCH

"Default architecture is i386, options are alpha and ppc"

"i386"

always

HAVE_MOVNTI

"This cpu supports the MOVNTI directive"

0

always

CROSS_COMPILE

"Cross compiler prefix"

""

always

CC

"Target C Compiler"

"$(CROSS_COMPILE)gcc"

always

HOSTCC

"Host C Compiler"

"gcc"

always

CPU_OPT

"Additional per-cpu CFLAGS"

none

used

OBJCOPY

"Objcopy command"

"$(CROSS_COMPILE)objcopy --gap-fill 0xff"

always

COREBOOT_VERSION

"coreboot version"

"2.0.0"

always

"\"%s\""

COREBOOT_EXTRA_VERSION

"\"%s\""

COREBOOT_BUILD

"Build date"

"$(shell date)"

always

"\"%s\""

COREBOOT_COMPILE_TIME

"Build time"

"$(shell date +%T)"

always

"\"%s\""

COREBOOT_COMPILE_BY

"Who build this image"

"$(shell whoami)"

always

"\"%s\""

COREBOOT_COMPILE_HOST

"Build host"

"$(shell hostname)"

always

"\"%s\""

COREBOOT_COMPILE_DOMAIN

"Build domain name"

"$(shell dnsdomainname)"

always

"\"%s\""

COREBOOT_COMPILER

"Build compiler"

"$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"

always

"\"%s\""

COREBOOT_LINKER

"Build linker"

"$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"

always

"\"%s\""

COREBOOT_ASSEMBLER

"Build assembler"

"$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"

always

"\"%s\""

CONFIG_CHIP_CONFIGURE

"Use new chip_configure method for configuring (non-pci) devices"

0

used

CONFIG_USE_INIT

"Use stage 1 initialization code"

0

always

HAVE_FALLBACK_BOOT

"Set if fallback booting required"

0

always

"%d"

HAVE_FAILOVER_BOOT

"Set if failover booting required"

0

always

"%d"

USE_FALLBACK_IMAGE

"Set to build a fallback image"

0

used

"%d"

USE_FAILOVER_IMAGE

FALLBACK_SIZE

"Default fallback image size"

65536

used

"0x%x"

FAILOVER_SIZE

ROM_SIZE

"Size of your ROM"

none

used

"0x%x"

ROM_IMAGE_SIZE

"Default image size"

65535

always

"0x%x"

ROM_SECTION_SIZE

"Default rom section size"

{FALLBACK_SIZE}

used

"0x%x"

ROM_SECTION_OFFSET

"Default rom section offset"

{ROM_SIZE - FALLBACK_SIZE}

used

"0x%x"

PAYLOAD_SIZE

"Default payload size"

{ROM_SECTION_SIZE - ROM_IMAGE_SIZE}

always

"0x%x"

_ROMBASE

"Base address of coreboot in ROM"

{PAYLOAD_SIZE}

always

"0x%x"

_ROMSTART

"Start address of coreboot in ROM"

none

used

"0x%x"

_RESET

"Hardware reset vector address"

{_ROMBASE}

always

"0x%x"

_EXCEPTION_VECTORS

"Address of exception vector table"

{_ROMBASE+0x100}

always

"0x%x"

STACK_SIZE

"Default stack size"

0x2000

always

"0x%x"

HEAP_SIZE

"Default heap size"

0x2000

always

"0x%x"

_RAMBASE

"Base address of coreboot in RAM"

none

always

"0x%x"

_RAMSTART

"Start address of coreboot in RAM"

none

used

"0x%x"

USE_DCACHE_RAM

"Use data cache as temporary RAM if possible"

0

always

CAR_FAM10

"AMD family 10 CAR requires additional setup"

0

always

DCACHE_RAM_BASE

"Base address of data cache when using it for temporary RAM"

0xc0000

always

"0x%x"

DCACHE_RAM_SIZE

"Size of data cache when using it for temporary RAM"

0x1000

always

"0x%x"

DCACHE_RAM_GLOBAL_VAR_SIZE

"Size of region that for global variable of cache as ram stage"

0

always

"0x%x"

CONFIG_AP_CODE_IN_CAR

MEM_TRAIN_SEQ

WAIT_BEFORE_CPUS_INIT

XIP_ROM_BASE

"Start address of area to cache during coreboot execution directly from ROM"

0

used

"0x%x"

XIP_ROM_SIZE

"Size of area to cache during coreboot execution directly from ROM"

0

used

"0x%x"

CONFIG_COMPRESS

"Set for compressed image"

1

always

CONFIG_UNCOMPRESSED

"Set for uncompressed image"

{!CONFIG_COMPRESS}

always

"%d"

CONFIG_LB_MEM_TOPK

"Kilobytes of memory to initialized before executing code from RAM"

2048

always

"%d"

HAVE_OPTION_TABLE

"Export CMOS option table"

0

always

USE_OPTION_TABLE

"Use option table"

{HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}

always

"%d"

LB_CKS_RANGE_START

"First CMOS byte to use for coreboot options"

49

always

"%d"

LB_CKS_RANGE_END

"Last CMOS byte to use for coreboot options"

125

always

"%d"

LB_CKS_LOC

"Pair of bytes to use for CMOS checksum"

126

always

"%d"

CRT0

"Main initialization target"

"$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"

always

DEBUG

"Enable debugging code"

1

always

CONFIG_CONSOLE_VGA

"Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"

0

always

CONFIG_CONSOLE_VGA_MULTI

CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST

CONFIG_CONSOLE_BTEXT

CONFIG_CONSOLE_LOGBUF

"Log messages to buffer"

0

always

CONFIG_CONSOLE_SROM

"Log messages to SROM console"

0

always

CONFIG_CONSOLE_SERIAL8250

"Log messages to 8250 uart based serial console"

0

always

CONFIG_USBDEBUG_DIRECT

"Log messages to ehci debug port console"

0

always

DEFAULT_CONSOLE_LOGLEVEL

"Console will log at this level unless changed"

7

always

MAXIMUM_CONSOLE_LOGLEVEL

8

always

CONFIG_SERIAL_POST

"Enable SERIAL POST codes"

0

always

NO_POST

"Disable POST codes"

none

used

TTYS0_BASE

"Base address for 8250 uart for the serial console"

0x3f8

always

"0x%x"

TTYS0_BAUD

"Default baud rate for serial console"

115200

always

TTYS0_DIV

"Allow UART divisor to be set explicitly"

none

used

"%d"

TTYS0_LCS

"Default flow control settings for the 8250 serial console uart"

0x3

always

"0x%x"

CONFIG_USE_PRINTK_IN_CAR

"use printk instead of print in CAR stage code"

0

always

MAINBOARD

"Mainboard name"

"Mainboard_not_set"

always

MAINBOARD_PART_NUMBER

"Part number of mainboard"

"Part_number_not_set"

always

"\"%s\""

MAINBOARD_VENDOR

"Vendor of mainboard"

"Vendor_not_set"

always

"\"%s\""

MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID

"PCI Vendor ID of mainboard manufacturer"

0

always

MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID

"PCI susbsystem device id assigned my mainboard manufacturer"

0

always

"0x%x"

MAINBOARD_POWER_ON_AFTER_POWER_FAIL

"Default power on after power fail setting"

none

used

CONFIG_SYS_CLK_FREQ

"System clock frequency in MHz"

none

used

CONFIG_MAX_PCI_BUSES

"Maximum number of PCI buses to search for devices"

255

always

CONFIG_SMP

"Define if we support SMP"

0

always

CONFIG_MAX_CPUS

CONFIG_MAX_PHYSICAL_CPUS

CONFIG_LOGICAL_CPUS

"Should multiple cpus per die be enabled?"

0

always

HAVE_MP_TABLE

"Define to build an MP table"

none

used

SERIAL_CPU_INIT

APIC_ID_OFFSET

"We need to share this value between cache_as_ram_auto.c and northbridge.c"

0

always

ENABLE_APIC_EXT_ID

"Enable APIC ext id mode 8 bit"

0

always

LIFT_BSP_APIC_ID

"decide if we lift bsp apic id while ap apic id"

0

always

CONFIG_IDE_PAYLOAD

"Boot from IDE device"

0

always

CONFIG_ROM_PAYLOAD

"Boot image is located in ROM"

0

always

CONFIG_ROM_PAYLOAD_START

"ROM stream start location"

{0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}

always

"0x%x"

CONFIG_COMPRESSED_PAYLOAD_NRV2B

"NRV2B compressed boot image is located in ROM"

0

always

CONFIG_COMPRESSED_PAYLOAD_LZMA

"LZMA compressed boot image is located in ROM"

0

always

CONFIG_PRECOMPRESSED_PAYLOAD

"boot image is already compressed"

0

always

CONFIG_SERIAL_PAYLOAD

"Download boot image from serial port"

0

always

CONFIG_FS_PAYLOAD

"Boot from a filesystem"

0

always

CONFIG_FS_EXT2

"Enable ext2 filesystem support"

0

always

CONFIG_FS_ISO9660

"Enable ISO9660 filesystem support"

0

always

CONFIG_FS_FAT

"Enable FAT filesystem support"

0

always

AUTOBOOT_DELAY

"Delay (in seconds) before autobooting"

2

always

AUTOBOOT_CMDLINE

"Default command line when autobooting"

"hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"

always

"\"%s\""

USE_WATCHDOG_ON_BOOT

"Use the watchdog on booting"

0

always

CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT

"Enable support for plugin Hypertransport busses"

1

always

CONFIG_AGP_PLUGIN_SUPPORT

"Enable support for plugin AGP busses"

1

always

CONFIG_CARDBUS_PLUGIN_SUPPORT

"Enable support cardbus plugin cards"

1

always

CONFIG_PCIX_PLUGIN_SUPPORT

"Enable support for plugin PCI-X busses"

1

always

CONFIG_PCIEXP_PLUGIN_SUPPORT

"Enable support for plugin PCI-E busses"

1

always

HAVE_PIRQ_TABLE

"Define if we have a PIRQ table"

none

used

IRQ_SLOT_COUNT

"Number of IRQ slots"

none

used

CONFIG_PCIBIOS_IRQ

"PCIBIOS IRQ support"

none

used

CONFIG_IOAPIC

"IOAPIC support"

none

used

CONFIG_IDE

"Define to include IDE support"

0

always

IDE_BOOT_DRIVE

"Disk number of boot drive"

0

always

IDE_SWAB

"Swap bytes when reading from IDE device"

none

used

IDE_OFFSET

"Sector at which to start searching for boot image"

0

always

PCI_IO_CFG_EXT

"allow 4K register space via io CFG port"

0

always

PCIC0_CFGADDR

"Address of PCI Configuration Address Register"

none

used

"0x%x"

PCIC0_CFGDATA

"Address of PCI Configuration Data Register"

none

used

"0x%x"

ISA_IO_BASE

"Base address of PCI/ISA I/O address range"

none

used

"0x%x"

ISA_MEM_BASE

"Base address of PCI/ISA memory address range"

none

used

"0x%x"

PNP_CFGADDR

"PNP Configuration Address Register offset"

none

used

"0x%x"

PNP_CFGDATA

"PNP Configuration Data Register offset"

none

used

"0x%x"

_IO_BASE

"Base address of memory mapped I/O operations"

none

used

"0x%x"

EMBEDDED_RAM_SIZE

"Embedded boards generally have fixed RAM size"

none

used

CONFIG_CHIP_NAME

"Compile in the chip name"

0

always

CONFIG_GDB_STUB

"Compile in gdb stub support?"

0

used

HAVE_INIT_TIMER

"Have a init_timer function"

0

always

HAVE_HARD_RESET

"Have hard reset"

none

used

MEMORY_HOLE

"Set to deal with memory hole"

none

used

MAX_REBOOT_CNT

"Set maximum reboots"

3

always

CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2

"Use timer2 to callibrate the x86 time stamp counter"

0

used

INTEL_PPRO_MTRR

""

none

used

CONFIG_UDELAY_TSC

"Implement udelay with the x86 time stamp counter"

0

used

CONFIG_UDELAY_IO

"Implement udelay with x86 io registers"

0

used

FAKE_SPDROM

"Use this to fake spd rom values"

0

always

HAVE_ACPI_TABLES

"Define to build ACPI tables"

0

always

ACPI_SSDTX_NUM

"extra ssdt num for PCI Device"

0

always

AGP_APERTURE_SIZE

"AGP graphics virtual memory aperture size"

none

used

"0x%x"

HT_CHAIN_UNITID_BASE

"this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"

1

always

HT_CHAIN_END_UNITID_BASE

SB_HT_CHAIN_UNITID_OFFSET_ONLY

SB_HT_CHAIN_ON_BUS0

PCI_BUS_SEGN_BITS

MMCONF_SUPPORT

"enable mmconfig for pci conf"

0

always

MMCONF_SUPPORT_DEFAULT

"enable mmconfig for pci conf"

0

always

HW_MEM_HOLE_SIZEK

HW_MEM_HOLE_SIZE_AUTO_INC

CONFIG_VAR_MTRR_HOLE

"using hole in MTRR instead of increasing method"

1

always

K8_HT_FREQ_1G_SUPPORT

"Optern E0 later could support 1G HT, but still depends MB design"

0

always

K8_REV_F_SUPPORT

CBB

"Opteron cpu bus num base"

0

always

CDB

"Opteron cpu device num base"

0x18

always

HT3_SUPPORT

"Hypertransport 3 support, include ac HT and unganged sublink feature"

0

always

EXT_RT_TBL_SUPPORT

"support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"

0

always

EXT_CONF_SUPPORT

"support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"

0

always

DIMM_SUPPORT

"0x%x"

CPU_SOCKET_TYPE

"cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"

0x10

always

CPU_ADDR_BITS

"CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"

36

always

CONFIG_VGA_ROM_RUN

"Init x86 ROMs on VGA-class PCI devices"

0

always

CONFIG_PCI_ROM_RUN

"Init x86 ROMs on all PCI devices"

0

always

CONFIG_PCI_64BIT_PREF_MEM

CONFIG_AMDMCT

"use AMD MCT to init RAM instead of native code"

0

always

CONFIG_VIDEO_MB

CONFIG_SPLASH_GRAPHIC

"Paint a splash screen"

0

used

CONFIG_GX1_VIDEO

"Build in GX1's graphic support"

0

used

CONFIG_GX1_VIDEOMODE

"Define video mode after reset"

none

used

CONFIG_SANDPOINT_ALTIMUS

"Configure Sandpoint with Altimus PMC"

0

never

CONFIG_SANDPOINT_TALUS

"Configure Sandpoint with Talus PMC"

0

never

CONFIG_SANDPOINT_UNITY

"Configure Sandpoint with Unity PMC"

0

never

CONFIG_SANDPOINT_VALIS

"Configure Sandpoint with Valis PMC"

0

never

CONFIG_SANDPOINT_GYRUS

"Configure Sandpoint with Gyrus PMC"

0

never

CONFIG_BRIQ_750FX

"Configure briQ with PowerPC 750FX"

0

never

CONFIG_BRIQ_7400

"Configure briQ with PowerPC G4"

0

never

Retrieved from "https://www.coreboot.org/index.php?title=Coreboot_Options&oldid=5650"