Easy projects: Difference between revisions
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If you're a coreboot or flashrom newbie, this page is for you. | If you're a coreboot or flashrom newbie, this page is for you. | ||
= flashrom = | |||
The [[flashrom]] tool can read/write coreboot/BIOS images from/to flash chips. | The [[flashrom]] tool can read/write coreboot/BIOS images from/to flash chips. | ||
== Add timing info to flash chip definitions == | |||
Go through the list of flash chips in flashchips.c inside the flashrom source. For each chip (except SPI chips), read through the data sheets and add a comment to the flash chip definition which contains the timing information in microseconds(!) for the probe sequence. | Go through the list of flash chips in flashchips.c inside the flashrom source. For each chip (except SPI chips), read through the data sheets and add a comment to the flash chip definition which contains the timing information in microseconds(!) for the probe sequence. | ||
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Every annotated chip helps. | Every annotated chip helps. | ||
== Add the bus type to flash chip definitions == | |||
Go through the list of flash chips in flashchips.c inside the flashrom source. Look for chip definitions which have .bustype = CHIP_BUSTYPE_NONSPI and look at their data sheets. Read the data sheets and try to figure out the flash bus they use (Parallel/LPC/FWH/SPI). Change the bustype field to CHIP_BUSTYPE_PARALLEL etc. and post a patch to the list. | Go through the list of flash chips in flashchips.c inside the flashrom source. Look for chip definitions which have .bustype = CHIP_BUSTYPE_NONSPI and look at their data sheets. Read the data sheets and try to figure out the flash bus they use (Parallel/LPC/FWH/SPI). Change the bustype field to CHIP_BUSTYPE_PARALLEL etc. and post a patch to the list. | ||
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[[Flashrom#Communication_bus_protocol]] has a writeup on how to figure out the bus type. | [[Flashrom#Communication_bus_protocol]] has a writeup on how to figure out the bus type. | ||
== Add new flash chip definitions == | |||
We have a few dozen chip IDs listed in flash.h, but not in flashchips.c. Find them, dig up the data sheets and add chip definitions for them to flashchips.c. You can use similar flash chips as a guideline. | We have a few dozen chip IDs listed in flash.h, but not in flashchips.c. Find them, dig up the data sheets and add chip definitions for them to flashchips.c. You can use similar flash chips as a guideline. | ||
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Every added chip broadens flashrom support. | Every added chip broadens flashrom support. | ||
== Test flashrom == | |||
If you have a desktop (no laptops/notebooks/netbooks), please run | If you have a desktop (no laptops/notebooks/netbooks), please run | ||
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to the coreboot [[Mailinglist|mailing list]] (preferred) or to [mailto:flashrom@coreboot.org flashrom@coreboot.org] | to the coreboot [[Mailinglist|mailing list]] (preferred) or to [mailto:flashrom@coreboot.org flashrom@coreboot.org] | ||
= coreboot = | |||
I'll skip explaining what coreboot is. The whole wiki is about this topic and I can't summarize it in one sentence. | I'll skip explaining what coreboot is. The whole wiki is about this topic and I can't summarize it in one sentence. | ||
== coreboot v2 == | |||
The workhorse version of coreboot. Lots of supported boards, but difficult to work with. | The workhorse version of coreboot. Lots of supported boards, but difficult to work with. | ||
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TODO: Add easy tasks here. | TODO: Add easy tasks here. | ||
== coreboot v3 == | |||
The next generation version of coreboot. Few supported boards, still in the design testing phase, easy to work with. | The next generation version of coreboot. Few supported boards, still in the design testing phase, easy to work with. | ||
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TODO: Add easy tasks here. | TODO: Add easy tasks here. | ||
= Payloads = | |||
coreboot can use a number of different [[Payloads|payloads]]. | coreboot can use a number of different [[Payloads|payloads]]. | ||
== Add/test new supported payloads == | |||
* Test syslinux (probably requires [[SeaBIOS]] in addition, needs to be checked). | * Test syslinux (probably requires [[SeaBIOS]] in addition, needs to be checked). | ||
* Port [[GPXE]] to "native" coreboot (it works fine together with [[SeaBIOS]] though). | * Port [[GPXE]] to "native" coreboot (it works fine together with [[SeaBIOS]] though). | ||
= Other = | |||
* Add support for using coreboot in VirtualBox. | * Add support for using coreboot in VirtualBox. | ||
Revision as of 14:39, 2 June 2009
You probably came here trying to find a small (minutes to hours) and easy task where you can get your hands dirty and get results immediately.
If you're a coreboot or flashrom newbie, this page is for you.
flashrom
The flashrom tool can read/write coreboot/BIOS images from/to flash chips.
Add timing info to flash chip definitions
Go through the list of flash chips in flashchips.c inside the flashrom source. For each chip (except SPI chips), read through the data sheets and add a comment to the flash chip definition which contains the timing information in microseconds(!) for the probe sequence.
This will make probing a lot more reliable.
Every annotated chip helps.
Add the bus type to flash chip definitions
Go through the list of flash chips in flashchips.c inside the flashrom source. Look for chip definitions which have .bustype = CHIP_BUSTYPE_NONSPI and look at their data sheets. Read the data sheets and try to figure out the flash bus they use (Parallel/LPC/FWH/SPI). Change the bustype field to CHIP_BUSTYPE_PARALLEL etc. and post a patch to the list.
This will make probing faster and more reliable.
Even a single updated chip helps.
Flashrom#Communication_bus_protocol has a writeup on how to figure out the bus type.
Add new flash chip definitions
We have a few dozen chip IDs listed in flash.h, but not in flashchips.c. Find them, dig up the data sheets and add chip definitions for them to flashchips.c. You can use similar flash chips as a guideline.
This will reduce the number of undetected chips.
Every added chip broadens flashrom support.
Test flashrom
If you have a desktop (no laptops/notebooks/netbooks), please run
flashrom
and check if it finds your flash chip. If it does and any of the operations are listed as unsupported, we'd like to hear about it. If your flash chip is not found, we'd like to hear about it as well.
In both cases, please send the output of
flashrom -V
to the coreboot mailing list (preferred) or to flashrom@coreboot.org
coreboot
I'll skip explaining what coreboot is. The whole wiki is about this topic and I can't summarize it in one sentence.
coreboot v2
The workhorse version of coreboot. Lots of supported boards, but difficult to work with.
TODO: Add easy tasks here.
coreboot v3
The next generation version of coreboot. Few supported boards, still in the design testing phase, easy to work with.
TODO: Add easy tasks here.
Payloads
coreboot can use a number of different payloads.
Add/test new supported payloads
- Test syslinux (probably requires SeaBIOS in addition, needs to be checked).
- Port GPXE to "native" coreboot (it works fine together with SeaBIOS though).
Other
- Add support for using coreboot in VirtualBox.