Board:nokia/ip530

This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.

front view

The Nokia IP530 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. The original is only capable of starting a FreeBSD FS. There is as far as I known no CD support in the orginal BIOS.

The System has no VGA, all console activity must be done through a serial console.

At the front the following can be found;

board view

• Power LED
• Alert LED
• Fault LED
• Primary IDE activity LED
• Secondary IDE activity LED
• Two drive bays (primary IDE and secondary IDE)
• 2 Serial interfaces COM1 and COM2
• 4 Ethernet RJ45 sockets
• 2 PCMCIA slots
• Reset button
• 3 Compact PCI slots (industial PCI)

At the back the following can be found;

• Power supply
  • EURO Power connector
  • Power switch
  • LED 'PWR OK'
  • LED 'FAULT'
  • LED 'OVR TEMP'
  • two FANs for power supply cooling
• Dual FAN unit
  • two FANs for mainboard cooling

Development status

The current development status is; Coreboot (Revision 6292) runs with seaBIOS (commit 89a1efd95c4f3ee349fa36c31526ae880820ce19). Linux 2.6.32 runs on the system, and most devices are supported. But there are still things to findout. Currently one IP530 runs as a server with Ubuntu 10.10.

The current coreboot works for board revision A of Nokia. Currently underway is the new release with autodetect support for board revision B and higher. Currently known the Nokia revisions go up to F. And revision F in known to work with coreboot implementation of revision B.

Hardware status

Device/functionality	Status	Comments
CPU
CPU works	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	PIII SL5DV (1000 / 256 / 133 / 1.75V)
L1 cache enabled	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	CPU: L1 I cache: 16K, L1 D cache: 16K
L2 cache enabled	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	L2 cache is standard for the P3-68X models
L3 cache enabled	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Multiple CPU support	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Multi-core support	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Hardware virtualization	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
RAM
EDO	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
SDRAM	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	upto 4 single sided 128Mb or 4 dual sided 256Mb
SO-DIMM	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
DDR	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
DDR2	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
DDR3	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Dual channel support	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
ECC support	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | WIP	Not yet supported by the coreboot 440BX code, but it's on our TODO list.
On-board Hardware
On-board IDE 3.5"	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Primary and secondary controllers, the primary controller has a Compact Flash slot attached on board, as primary drive.
On-board IDE 2.5"	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board SATA	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board SCSI	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board USB	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	The USB is not routed to any connector, u can be picked up from the board it self, there is an instruction below on this wiki-page how to do this
On-board VGA	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board Ethernet	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Four intel 21143PD controllers.
On-board Audio	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board Modem	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board FireWire	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board Smartcard reader	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board CompactFlash	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Is wrired are primary drive on primary IDE controller.
On-board PCMCIA	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Texas Instruments PCI1225 PCMCIA/Cardbus controller
On-board Wifi	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board Bluetooth	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
On-board SD card reader	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Add-on slots/cards
ISA add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Audio/Modem-Riser (AMR/CNR) cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Tested: With 4 Ethernet adapter card of Nokia (Compact-PCI slots)
Mini-PCI add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Mini-PCI-Express add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown
PCI-X add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
AGP graphics cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x1 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x2 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x4 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x8 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x16 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PCI Express x32 add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
HTX add-on cards	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Legacy / Super I/O
Floppy	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Serial port 1 (COM1)	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK
Serial port 2 (COM2)	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK
Parallel port	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PS/2 keyboard	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Internal 4 pin connector J-KBD
PS/2 mouse	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Game port	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Infrared	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
PC speaker	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
DiskOnChip	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Input
Trackpoint	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Touchpad	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Fn Hotkeys	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Fingerprint Reader	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Laptop
Docking VGA	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Docking LAN	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Docking USB	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Docking Audio	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Docking Displayport	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Thinklight	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Webcam	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Miscellaneous
Sensors / fan control	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | WIP
Hardware watchdog	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
SMBus	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | WIP
CAN bus	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
CPU frequency scaling	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Other powersaving features	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
ACPI	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | No	There's no ACPI implementation for this board, but it's on our TODO list.
Reboot	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Poweroff	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Suspend	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown
Nonstandard LEDs	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Special-purpose LEDs available on the board, Alert and Fault are controlled by the superio
High precision event timers (HPET)	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Random number generator (RNG)	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Wake on modem ring	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Wake on LAN	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Wake on keyboard	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
Wake on mouse	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | N/A
TPM	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | Unknown
Flashrom	OK=lime | TODO=red | No=red | WIP=orange | Untested=yellow | N/A=lightgray | yellow }}" | OK	Supported flashrom revision 1010 or higher.

System Setup

On board of the IP530 can be found the following:

• Pentium III.
• I440BX northbridge.
• 82371 southbridge.
• intel 21150 PCI to PCI bridge.
• 28F400, 512 Kbyte flashrom.
• SMSC FDC37B787 superio with 1024 bits SPI eeprom attached.
• LM78 power controller.
• 4 intel 21143PD ethernet controllers with KS8716 PHY interface, with each a 1024 bits SPI eeprom attached.
• Texas instruments PCI1225 PCMCIA/Cardbus controller with TPS22061 slot controller.
• 4 SD-RAM sockets.

Below the description is given for the following;

• For the connectors on the mainboard of the Nokia IP530, due missing documentation of the manufacturer.
• To create a flash option board on the J-DEBUG connector.
• To create a USB port.
• HOWTO read the status of the jumpers.
• HOWTO enable/disable the LEDs.
• The layout of the SPI eeprom behind the SuperIO.

---

J-DEBUG

The JDEBUG connector can be used for attaching an external ROM (flash chip) to the board for BIOS development.

JDEBUG connector

Pin#	Name	Description	Pin#	Name	Description
1	unknown	?	2	VCC +5 Volt	n/a
3	A16	Address line A16	4	A18	Address line A18
5	A15	Address line A15	6	A17	Address line A17
7	A12	Address line A12	8	A14	Address line A14
9	A7	Address line A7	10	A13	Address line A13
11	A6	Address line A6	12	A8	Address line A8
13	A5	Address line A5	14	A9	Address line A9
15	A4	Address line A4	16	A11	Address line A11
17	A3	Address line A3	18	OE#	Chip Enable Line OE#
19	A2	Address line A2	20	A10	Address line A10
21	A1	Address line A1	22	JP800.1	BIOSCS#
23	A0	Address line A0	24	D7	Data line D7
25	D0	Data line A0	26	D6	Data line D6
27	D1	Data line D1	28	D5	Data line D5
29	D2	Data line D2	30	D4	Data line D4
31	IOW#	Control line IOW#	32	D3	Data line D3
33	GND	Ground	34	IOR#	Control line IOR#

For recovery there can be placed an flashrom board on the J-DEBUG connector. Belowe here the schematic in PDF can be used.

Schematic ROM option board

As wel the PCB layout in PDF, for this print it on a transparant paper in the highest quality (so it will be very black). From this a PCB can be made.

Printed Circuit Board (PCB) layout

The 34 pin connector shoud be female 90 degres, so that the board is upright when attached to the IP530. you can select a 32 DIL socket, 32 PLCC socket, but not both flashroms inserted only one at the time.

The overview can be used to place the components and solder them in. The red lines in the overview are wires that need to be soldered in.

Components overview PCB

When ready flash the rom in a programmer and inserted it into a socket. Attach the board to the main board of the IP530 (notice the PIN 1 of both boards, when you put it wrong the flashrom on the option board will be blown-up.

---

Jumper JP800 - BIOSCS select

This jumper selected the on-board flash or the J-DEBUG connector where the BIOSCS# line is routed.

J800 Jumper

Pin#	Name	Description
1	JDEBUG.P22	This is connected to PIN 22 of the JDEBUG connection on the board
2	BIOSCS#	Connected to the ROMCS# line of the Northbridge
3	CS#	This is connected to CS# of the on-board flash chip.

The WP# line of the on-board flashchip is controlled by Pin39 of the SMSC FDC37B787 Super I/O chip.

On the production boards the J800 is not present and the R814 (0 Ohm) is placed, remove this resistor and solder in the 3 pin-jumper for JP800. And place the jumper on position 2-3 to select the on-board flash chip.

---

Jumper JP900

This is a input signal on the Super I/O chip.

J900 Jumper

Pin#	Name	Description
1	GND	Ground of the system
2	GPIO16	Pin 4 of the SMSC FDC37B787 Super I/O chip.

Pin 2 is pulled-up by resistor up VCC.

 #define REG_GP1x		0xF6
 #define JP900		        0x20
 
 sio_enter_config( 0x3F0 );
 val = (sio_read( 0x3F0, REG_GP6x ) & JP901);  
 sio_leave_config( 0x3F0 );

---

Jumper JP901

This is a input signal on the Super I/O chip.

J901 Jumper

Pin#	Name	Description
1	GND	Ground of the system
2	GPIO67	Pin 90 of the SMSC FDC37B787 Super I/O chip.

Pin 2 is pulled-up by resistor up VCC.

 #define REG_GP6x		0xYY
 #define JP901		        0x80
 
 sio_enter_config( 0x3F0 );
 val = (sio_read( 0x3F0, REG_GP6x ) & JP901);  
 sio_leave_config( 0x3F0 );

---

Jumper JKBD

JKBD Connector

Pin#	Name	Description
1	VCC	VCC +5 volt
2	DATA	The DAT line of the PS2 keyboard (pin 70 SMSC FDC37B787)
3	CLOCK	The CLK line of the PS2 keyboard (pin 71 SMSC FDC37B787)
4	GND	Ground of the system

---

Front LEDs

LEDs in front

LED	Control line	Description
Fault	FDC37B787-GP13	active low
Alert	FDC37B787-GP17	active low

 #define REG_GP1x		0xF6
 #define LED_FAULT		0x08
 #define LED_ALERT		0x80
 
 sio_enter_config( 0x3F0 );
 val = sio_read( 0x3F0, REG_GP1x );
 
 // To enable the ALERT led
 val &= ~LED_ALERT;
 
 // To disable the ALERT led
 val |= LED_ALERT;
 
 // To enable the FAULT led
 val &= ~LED_FAULT;
 
 // To disable the FAULT led
 val |= LED_FAULT;
 
 sio_write( 0x3F0, REG_GP1x, val );
 sio_leave_config( 0x3F0 );

By using the sio_xxx() functions from flashrom, makes easy work dis-/en-abling the LEDs in the front.

---

EEPROM behide the SuperIO

EEPROM information

address range	length	Content	Description
0x00-0x05	6 bytes	IP530\x00	Product name
0x06-0x13	14 bytes	0x55	Filler
0x14-0x17	4 bytes	0x05,0x00,0x00,0x00	Unknown
0x18-0x1B	4 bytes	0x04,0x00,0x00,0x00	Unknown
0x1C-0x1F	4 bytes	0x03,0x00,0x00,0x00	Unknown
0x20-0x23	4 bytes	0x10,0x00,0x00,0x00	Unknown
0x24-0x29	6 bytes	-	Board number, sticker close to the PIII cpu
0x2A-0x37	14 bytes	-	Mfg. P/n (on the bottom side of the unit), filled out with spaces
0x38-0x3D	6 bytes	0x55	Filler
0x3E-0x3F	2 bytes	0xYY,0x00	Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42
0x40-0x51	18 bytes	0x55	Filler
0x52-0x5D	12 bytes	-	Serial number (on the bottom side of the unit)
0x5E-0x7D	32 bytes	0x55	Filler
0x7E-0x7F	2 bytes	0xFF,0xFF	Unknown, probably the checksum value, but not used therefore filled 0xFFFF

On coreboot startup the eeprom is read, to determine if its a IP530, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision, revision B will be assumed.

Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.

---

USB Connections

This requires two wires to be soldered on the backside of the mainboard, pictures will be added later

Put the mainboard upside down, and the power connector facing you. Find the footprint of the 82371 southbridge. Locate the two pads; i directly above (about 1.5 mm) the F1 pin of the SB, and 1 to left (about 15mm) of the A5 pin of the SB.

Solder two wires to the two pads, be aware that the USB lines are polarity sensitive !!!

                 _____
 USBPxP >---+---|_____|---+---------> USBPx+ to connector pin 3
            |     27R     |
            |            ---      * VCC 5 volt
          ----- 27pF     | | 15K  |
          -----          | |      |
            |            | |      +-> to connector pin 1
            |            --- 
            |             | 
 * GND  >---+-------------+---------> to connector pin 4
            |     27R     |
            |            ---
          ----- 27pF     | | 15K
          -----          | |
            |            | |
            |            ---
            |    _____    |
 USBPxN >---+---|_____|---+---------> USBPx- to connector pin 2
                  27R
 * pickup from somewhere on the board the power lines VCC 5 volt and GND (for instance on the JKBD connector pin 1 for VCC and pin 4 for GND)

With this you have succesful added the USB port on the Nokia-IP530. Below are the schematic and board layout in .PDF format for the USB interface.

Schematic USB interface board

Printed Circuit Board (PCB) layout

Components overview PCB

---

Installing/booting the Nokia-IP530

The IP530 came with 8, 16 and 32Mb CF cards. There is available for download a 32Mb image that will start with the vendor bios. This image which can be placed on the standard CF card of the IP530.

 #[sudo] dd of=/dev/<cf-card-device> if=./linux-nokia-ip530-coreboot.img

Download 32Mb CF card image (7.9Mb)

This is not a distrubution, but a lean and mean installation with a stable kernel. This image is intended to be used for upgrading, testing and developing coreboot on a x86 system.

Place the CF card in the slot of the IP530, connect a serial cross cable. get a terminal program (like putty) set the speed to 115200 Bps None, 8, 1 and boot up the IP530.

You must get a prompt.

When installing Linux on/for a Nokia-IP530, there are two ways; 1 use a donor PC or installation of a distro that uses the serial console for its installation. The kernel boot customation, must be something like this "apci=off console=ttyS0,115200n8" apci=off is nessary due that the Nokia-IP530 coreboot bios does'nt support APCI yet. Make sure that the ttyS0 is enabled in inittab, or some other place depending on the distro.

---

Other OSes

It should be posible to run any OS that is able to run without the following devices:

• Videocard
• Keyboard
• Mouse
• Floppy
• Paralell port

OSes tested: Linux 2.6.32 and freeBSD 8.1 (unknown if all devices work as they work under Linux)

But NO windows :-)

---

Flashing

Depending on the board revision, the board revision can be found on the inside of the machine, its on little stickers on the right-side of the board. There are currently to revisions (A/B) available doe the IP530.

 coreboot-nokia-ip530-board-rev-a.rom
 
 coreboot-nokia-ip530-board-rev-b.rom

Both rom images are on the Download 32Mb CF card image (7.9Mb)

For flashing the images read the documentation of flashrom. You need atleast Revision 1010 of flashrom.

---

Feedback

Havefun with your Nokia-IP530, any remarks about this please email me on pe2mbs@yahoo.co.uk

You can mail me too if you have a board revision that is not supported yet, you must be able to load the rom image "coreboot-nokia-ip530-board-rev-b.rom", but be prepared that maybe not all hardware is working.

---

This work is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This work is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.