Board:google/butterfly
The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
See Chromebooks for additional details.
EHCI debug port
With the default settings, the USB port next to the HDMI connector is the EHCI debug port.
Building a complete coreboot image
Including the MAC address and keyboard layout
The coreboot that ships with the laptop will read the keyboard layout and MAC address from the flash. Since ChromeOS uses a different layout than CBFS, the region containing these parameters must me included in the CBFS of the custom coreboot. When not building for ChromeOS, coreboot will read this region from a CBFS file named vpd.bin.
Get 'flashmap'
$ git clone https://chromium.googlesource.com/chromiumos/third_party/flashmap
Find the RO_VPD section
Build flashmap, then run fmap_decode on the extracted chromebook firmware.
$ ./fmap_decode original_chrome_image.rom
Locate the RO_VPD section in the output:
area_offset="0x00600000" area_size="0x00004000" area_name="RO_VPD" area_flags_raw="0x01" area_flags="static"
Extract the RO_VPD section from ROM image.
First, convert area_offset and area_size to decimal, as dd does not accept hexadecimal input, then use dd to extract the RO_VPD section.
$ dd if=original_chrome_image.rom bs=1 skip=ibs=$((area_offset)) count=$((area_size)) of=vpd.bin
Insert vpd.bin in the custom coreboot image:
$ cbfstool build/coreboot.rom add -f vpd.bin -n vpd.bin -t raw