Board:emulation/spike-riscv

SPIKE is RISC-V's primary emulator. The Spike support in coreboot is mostly being developed by jn as part of his GSoC 2016.

Build instructions

These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the discussion page or IRC (or just fix it).

Building the toolchain

• clone the coreboot git repository
• download and apply this patch and this patch.
• run make crossgcc-riscv and a have a cup of $BEVERAGE

Building spike

• download Spike from https://github.com/riscv/riscv-isa-sim
• download and apply this patch that implements an 8250 UART
• TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes
• TODO: running make

Building coreboot without a payload

• TODO: patch patch patch
• run make menuconfig and select Emulation/SPIKE ucb riscv from the Mainboard menu
• run make
• run util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elf to create an ELF file (spike can only load ELF files)
• run spike build/coreboot.elf

For general spike usage, look at its GitHub page.

Building Linux

• git clone https://github.com/riscv/riscv-linux
• download linux 4.6.x from kernel.org
• cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .
• make ARCH=riscv defconfig
• make ARCH=riscv menuconfig, configure General setup/Cross-compiler tool prefix
• make ARCH=riscv

Building bbl

• TODO: libc stuff
• TODO: payload linker script foo
• TODO: patching the console output handler
• mkdir build
• cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld
• make

Building coreboot with bbl

• apply the same coreboot patches as above, and select Emulation/Spike ucb riscv
• in the Payload menu of menuconfig, select "ELF Payload" and enter the path to the bbl binary

Block devices currently missing

boot log

TODO