The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

Welcome! This is a collection on information to help you on your way to porting coreboot to an AMD Geode platform. Most of the information is about the Geode LX and CS5536 but may also be relevant to older versions of Geode. (Note that this does not cover the Geode NX).

If you find something incorrect or other deficiencies in this information please fix them!

Documentation

Development Guidelines
Developer Manual
Many Geode LX systems are based on the DB800 reference design, so that is a good place to start.
Geode LX CPU databook
Geode CS5536 Southbridge databook
Geode Linux webpage - The VSA and GeodeROM Porting guides are interesting.
Breaking the Chains -- Using LinuxBIOS to Liberate Embedded x86 Processors - was heavily influenced by the experience of the initial Geode LX port.

Build coreboot for Geode

Use buildrom. It can handle the payload and VSA for you.

$ svn co svn://coreboot.org/buildrom

Checkout coreboot:

$ svn co svn://coreboot.org/coreboot/trunk coreboot

Build a db800 for starters and set buildrom to build your local svn directory in menuconfig.

$ make menuconfig
$ make

From this point you can customize the db800 and then make the target, mainboard, and buildrom customization patches later.

Manual build

If you really want to get your hands dirty. Roll up your sleeves...

Get the current VSA binary, gpl_vsa_lx_102.bin, from the blobs git repository: git clone http://review.coreboot.org/p/blobs.git. The VSA code/binary can be found in blobs/cpu/amd/geode_lx/

Older versions like amd_vsa_lx_1.01.bin.gz are still available here and extract it. It will need to be compressed and padded to make the correct ROM size. For a typical Geode platform the binary should be 36KB. Calculate the padding as follows: 36864 - size of lx_vsa.nrv2b = padding. The current image requires padding of 3264.

Then, find a payload and build it.

$ cd coreboot/targets
$ ./buildtarget amd/db800
$ cd amd/db800/db800
$ cp /from/someplace/payloadx ./payload.elf
$ make
$ cp /from/someplace/gpl_vsa_lx_102.bin .
$ fallback/nrv2b e gpl_vsa_lx_102.bin lx_vsa.nrv2b
$ dd if=/dev/zero of=padding bs=1 count=3264 
$ cat lx_vsa.nrv2b padding > lx_vsa.36k.bin
$ cat lx_vsa.36k.bin db800.rom > amd-db800.rom

You should now have a 512KB ROM image. You should be able to use flashrom or a ROM programmer to get the image onto your system. (Be prepared to brick it...)

The current GPL VSA source is hosted by coreboot.org, http://review.coreboot.org/gitweb?p=blobs.git;a=tree. The original source is still available on laptop.org.

Although not currently functional: OpenVSA aims to provide VSA buildable with open tools.

Porting

Now that you are building Geode coreboot images you are ready to make customizations to your platform. Most customizations can be handled in the mainboard directory.

$ cd coreboot-v2/src/mainboard/amd/db800

Make yourself familiar with this directory. There are not too many files.

IRQ routing

Almost every platform will require customization of the PIR table in irq_table.c.

Make yourself familiar with the PIR table specification.

If you have the motherboard schematics adjusting the table is fairly simple.

First check how many on board devices (including PCI slots) and update IRQ_SLOT_COUNT in Options.lb. Remember any time you change Options.lb or Config.lb you need to redo ./buildtarget.

Next check the INT lines (GPIOs) into the CS5536.

CS5536
line	CS5536 signal/pin
PCI$INTA_X	GPIO0 / INTA_L
PCI$INTB_X	GPIO7 / INTB_X
PCI$INTC_X	GPIO12 / INTR
PCI$INTD_X	GPIO13 / 8MI_L

Based on this information you can setup the

register "enable_gpio_int_route" = "0x0D0C0700"

line in Config.lb.

For each motherboard device check the INT pins. For example a PCI slot would look something like this:

PCI slot
pin	device	line
pin A6	INTA_X	PCI$INTB_X
pin A7	INTC_X	PCI$INTD_X
pin B7	INTB_X	PCI$INTC_X
pin B8	INTD_X	PCI$INTA_X

Take a closer look at irq_tables.c. L_PIRQA is the chipset incoming IRQ line and M_PIRQA is the bitmap of IRQ numbers it can generate. These should not change. You can adjust the IRQs generated by changing PIRQA etc. Yes, it is fine if they all share 10 or 11 but it might be easier to debug if they all have a different IRQ.

The table entries are the slot/device IRQ lines. I will break one entry down.

/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},   /* cpu */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},   /* ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */

I will break the last entry down.

0x00, (0x0E << 3) | 0x0 — slot(device) address (IDSEL)
{L_PIRQC, M_PIRQC} — slot INT line A to chipset INT line C (L_PIRQC), it can generate IRQs (M_PIRQC)
{L_PIRQD, M_PIRQD} — slot INT line B to chipset INT line C (L_PIRQD), it can generate IRQs (M_PIRQD)
{L_PIRQA, M_PIRQA} — slot INT line C to chipset INT line A...
{L_PIRQB, M_PIRQB} — slot INT lineD to chipset INT line B...
0x1 — arbitrary slot number
0x0 — rfu, always 0

If you don't have the schematics you will have to figure out the routing on your own. With lspci output and some trial and error you can figure it out. IRC or the mailing list is a good place to get help if you are stuck.

There's also a wiki entry on figuring out the routing table.

LPC Serial IRQs

IRQs from LPC need to be passed to the SC5536 PIC. It is important to only enable the expected sources and to configure the polarity. Enables are a bit mask. It depends on the SIO but typically, the polarity is the inverse of the enables as you can see in the example below. (Note that the Geode MFGPT driver uses IRQ7 by default. That will conflict with LPC SIRQ for the LPT port if you require it.)

Config.lb -

# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1"

Memory

On some systems the memory is soldered down and there is no SPD (Serial Presence Detect) which is required to properly setup DDR memory. In this case you will need to provide an SPD values in coreboot. This should be done by customizing spd_read_byte() in cache_as_ram_auto.c to do a table lookup. A good example can be found in src/mainboard/pcengines/alix1c/cache_as_ram_auto.c.

Power button

By default the CS5536 code sets the power button up for the 4 second soft off setting. If your system is booting and shuts off after four seconds check for a power button enable jumper. If your system doesn't have a power button and comes on when plugged in you will need to adjust the power button MSR. This is best done in cache_as_ram_main() in cache_as_ram_auto.c after the call to cs5536_early_setup(). The MSR name is PM Fail-Safe Delay and Enable (PM_FSD). (Yes, this could be made a Config.lb option)

Add the following line:

outl(0x00, PMS_IO_BASE + 0x40); // disable the power button

Graphics

For Geode graphics, use the upstreamed Geode framebuffer driver and the Geode X driver. There is no VGA ROM for Geode at this time.

Debug

Serial Output

The Geode CS5536 has two serial ports but on many mainboards the SIO serial ports are used instead. Setup Config.lb and the serial initialization depending on the configuration of the mainboard.

Config.lb -

register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "1"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"

In this case "1" enables the CS5536 serial port and the address and irq are setup to these values. The other important part of serial output is to setup the ports very early. This is done in cache_as_ram_main().

For an example of using the SIO serial ports instead of the CS5536, see the DB800 mainboard.

Dump System Configuration

print_conf() in src/northbridge/amd/lx/northbridge.c can help provide a good picture of the system configuration and should be one of the first tools you use to debug memory or other configuration issues.

Other

What are we missing?

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AMD Geode Porting Guide