AMD XHCI

From coreboot
Revision as of 20:39, 23 December 2013 by Ruik (talk | contribs) (Created page with "== AMD XHCI == The AMD XHCI controller in Hudson chip seems to be IP Core of Renesas uPD720200/200A. It looks the firmware consists of multi parts: {| |+ XHCI firmware layou...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

AMD XHCI

The AMD XHCI controller in Hudson chip seems to be IP Core of Renesas uPD720200/200A. It looks the firmware consists of multi parts:

XHCI firmware layout header 0xe bytes
Offset Size in bytes What
0x0000 2 Signature 0xaa55
0x0002 2 Offset to the BCD
0x0004 2 BCD size
0x0006 2 Offset to Main FW
0x0008 2 Main FW size
0x000a 2 Offset to the ACD
0x000c 2 Offset to the ACD
Main FW
Offset Size in bytes What
0x0000 2 Firmware version - 0x3032 means 3.0.3.2
0x0002 - Firmware data, most likely V850 controller
Retrieved from "https://www.coreboot.org/index.php?title=AMD_XHCI&oldid=12608"