Glossary
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Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
A
ACPI
The Advanced Configuration & Power Interface is an industry standard for letting the OS control power management.
- http://www.acpi.info/
- http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Configuration%20and%20Power%20Interface
AGP
Advanced Graphics Port
AGP Aperture
The memory range that is set aside for AGP access.
AHCI
The Advanced Host Controller Interface. Describes the register-level interface for a SATA host controller.
APIC
Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.
- http://www.computer-dictionary-online.org/index.asp?q=Advanced%20Programmable%20Interrupt%20Controller
- http://osdev.berlios.de/pic.html
B
BAR
Base Address Register (on PCI device).
BIOS
Basic Input/Output System.
C
CAR
Cache as RAM.
CMOS
Complementary metal oxyde semiconductor.
CPU
Central processing unit (e.g. an Athlon64)
D
DCR
Decode Control Register.
DID
Device ID, a way of identifying the hardware in question. See VID for more info.
DMA
Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
E
EEPROM
Electrically erasable programmable ROM (common mistake: electrical erasable programmable ROM).
EHCI
Enhanced Host Controller Interface (USB host controller).
F
Flashing
Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.
Framebuffer
The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:
- Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
- On-screen, meaning that the framebuffer is directly coupled to the visible display
G
GART
Graphics Address Relocation Table.
GATT
Graphics Aperture Translation Table.
GPIO
General Purpose Input/Output.
GSoC
H
Hypertransport
A high-speed electrical interconnection protocol between CPU, memory and peripheral devices.
I
I2C
Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control.
IDSEL/AD
Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
IRQ
Interrupt ReQuest (Handler).
J
JTAG
Debugging and test 4-wire interface named after an organization which defined it.
L
LPC
Low Pin Count, an interface aimed at replacing the ISA bus.
LRU
Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
M
MII
Media Independent Interface. This is a chip commonly found on ethernet devices, together with a PHY.
MMIO
Memory-mapped I/O and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
MPTable
Multi Processor Table. Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
MTRR
Memory Type Range Register. This can be used to control the way a processor accesses memory ranges.
O
OHCI
Open Host Controller Interface. IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel).
P
PAM
Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.
PAT
Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
- http://www.intel.com/design/pentium4/manuals/index_new.htm
- http://66.102.9.104/search?q=cache:k5pI7x36u1kJ:www-gtr.iutv.univ-paris13.fr/Cours/Mat/Architecture/Docs/System.pdf+%22page+attribute+table%22&hl=en&start=10
PAT
Performance Acceleration Technology.
PCI
Peripheral Component Interconnect.
PCI Configuration Space
PCI Express / PCIe
PHY
PHY layer device. A device that provides low level access to the physical layer.
PIC
A Programmable Interrupt Controller is a device to control peripheral devices, offloading the main CPU.
- http://www.computer-dictionary-online.org/index.asp?q=programmable%20interrupt%20controller
- http://www.interq.or.jp/japan/se-inoue/e_pic1.htm
PIO
Programmed Input/Output interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
PIR
Programmable Interrupt Routing?
PIRQ
PCI IRQ routing table,
- http://www.microsoft.com/whdc/archive/pciirq.mspx
- http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148
- http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm
- Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
PLCC
Plastic Leaded Chip Carrier, a square surface-mount chip package.
PLL
Phase Locked Loop is a device to keep (electrical) signals synchronised throughout the system.
POST
The Power On Self Test is a test to check that devices the computer will rely on are functioning, and initializes devices.
R
RDMA
Remote Direct Memory Access is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
RCS
Revision control systems.
S
SB
Southbridge. Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...
SBA
SideBand Addressing.
Shadow RAM
RAM which content is copied from ROM residing at the same address for speedup purposes.
SIO
Serial Input/Output.
SMBus
The System Management Bus is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
- http://www.smbus.org/
- http://www.computer-dictionary-online.org/index.asp?q=System%20Management%20Bus
SMM
System Management Mode. Processor mode that is mainly used for power management purposes.
SMRAM
System Management Random Access Memory.
SPD
Serial Presence Detect. On every (?) memory module there's an EPROM that provides the BIOS with information on how to properly configure the memory module.
SPI
The Serial Peripheral Interface Bus is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
SuperIO
The SuperIO is the chip that provides floppy, serial and parallel functionality/ports.
T
TLB
Translation Lookaside Buffer. The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
- http://www.linuxelectrons.com/article.php/20031021142247752
- For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
U
UC
Strong UnCacheable. Memory type setting in MTRR/PAT.
UC
UnCacheable. Memory type setting in MTRR/PAT.
- For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
UHCI
Universal Host Controller Interface. USB standard.
V
VGAcon
The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).
VID
Vendor ID, a way of identifying the hardware manufacturer.
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.
VMEBus
VERSAmodule Eurocard Bus or Versa Module Europa Bus. A computer bus originally developed for the Motorola 68000.
W
WB
Write-Back. Memory type setting in MTRR/PAT.
WC
Write-Combining. Memory type setting in MTRR/PAT.
WP
Write Protected. Memory type setting in MTRR/PAT.
WT
Write-Through. Memory type setting in MTRR/PAT.
- For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3