Shuttle SN25P Build Tutorial/Infos

From coreboot
Revision as of 19:59, 9 September 2008 by Vince (talk | contribs) (sections)
Jump to navigation Jump to search

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

/proc/interrupts

           CPU0
  0:        136   IO-APIC-edge      timer
  1:         12   IO-APIC-edge      i8042
  2:          0    XT-PIC-XT        cascade
  3:     280708   IO-APIC-fasteoi   eth1
  4:        292   IO-APIC-edge
  5:          0   IO-APIC-fasteoi   ICE1724
  7:          1   IO-APIC-edge
  8:          0   IO-APIC-edge      rtc0
 10:          2   IO-APIC-fasteoi   sata_nv, ehci_hcd:usb1
 11:         23   IO-APIC-fasteoi   sata_nv, ohci_hcd:usb2
 12:          2   IO-APIC-fasteoi   ohci1394
 14:       1933   IO-APIC-edge      pata_amd
 15:          0   IO-APIC-edge      pata_amd
283:          6   PCI-MSI-edge      eth0
NMI:          0   Non-maskable interrupts
LOC:    2809174   Local timer interrupts
TRM:          0   Thermal event interrupts
THR:          0   Threshold APIC interrupts
SPU:          0   Spurious interrupts
ERR:          1

getpir

mptable

superiotool -dV

flashrom -V

lspci -tnvv

lspci -vvvxx

setpci

  • setpci -s 0:0:1.0 7c.L
  • setpci -s 0:0:1.0 80.L
  • setpci -s 0:0:1.0 84.L

dmidecode

Retrieved from "https://www.coreboot.org/index.php?title=Shuttle_SN25P_Build_Tutorial/Infos&oldid=7075"